IP Library Granted Patent US 8,824,076
Granted Patent B2
US 8,824,076 · App. 13/597,046 · Granted Sep 2, 2014

Systems and methods for NPML calibration

Inventors: Lu Pan (Milpitas, CA); Seongwook Jeong (Sunnyvale, CA); Haitao Xia (San Jose, CA)
Assignee: LSI Corporation
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Quick Facts
Patent No.
US 8,824,076
App. No.
13/597,046
Granted
Sep 2, 2014
Kind
B2
Abstract

The present invention is related to systems and methods for adaptive parameter modification in a data processing system.

Claims (45)

1. A data processing system, the data processing system comprising:

a first noise predictive filter circuit, wherein operation of the first noise predictive filter circuit is based at least in part on a first coefficient set;

a second noise predictive filter circuit, wherein operation of the second noise predictive filter circuit is based at least in part on a second coefficient set; and

a forced variance filter coefficient adaptation circuit operable to adapt the first coefficient set and the second coefficient set while constraining at least one of a first variance of the first coefficient set and a second variance of the second coefficient set to a defined variance.

2. The data processing system of claim 1 , wherein adapting the first coefficient set and the second coefficient set includes constraining the first variance to the defined variance, and normalizing the second coefficient set such that the second variance is approximately equal to the first variance.

3. The data processing system of claim 1 , wherein adapting the first coefficient set and the second coefficient set includes modifying the first coefficient set while constraining the first variance to the defined variance, and modifying the second coefficient set while constraining the second variance to the defined variance.

4. The data processing system of claim 1 , wherein the first noise predictive filter circuit and the second noise predictive filter circuit are included in a data detection circuit, and wherein the data detection circuit further comprises:

a data detector circuit operable to apply a data detection algorithm guided by a first filtered output from the first noise predictive filter circuit and a second filtered output from the second noise predictive filter circuit, wherein the data detection algorithm includes a branch metric calculation performed without relying on the first variance and the second variance.

5. The data processing system of claim 4 , wherein the data detection algorithm is a Viterbi data detection algorithm.

6. The data processing system of claim 4 , wherein the defined variance is selected such that the branch metric calculation can be done without the first variance and the second variance.

7. The data processing system of claim 4 , wherein the data processing system further comprises:

a data decoder circuit operable to apply a data decoding algorithm to the detected output to yield a decoded output.

8. The data processing system of claim 7 , wherein the data decoding algorithm is a low density parity check algorithm.

9. The data processing system of claim 4 , wherein the first coefficient set is updated to the first noise predictive filter circuit and the second coefficient set is updated to the second noise predictive filter circuit using a coefficient update circuit operable to maintain the first coefficient set and the second coefficient set between data sets processed by the data detector circuit.

10. The data processing system of claim 1 , wherein the data processing system is implemented as part of a device selected from a group consisting of: a storage device and a receiving device.

11. The data processing system of claim 1 , wherein the data processing system is implemented as part of an integrated circuit.

12. A method, the method comprising:

adaptively calculating a first coefficient set, wherein a variance of the first coefficient set is forced to a defined variance;

adaptively calculating a second coefficient set;

applying the first coefficient set to a first noise predictive filter circuit, wherein operation of the first noise predictive filter circuit is governed at least in part based on the first coefficient set; and

applying a filter control derived from the second coefficient set to a second noise predictive filter circuit, wherein operation of the second noise predictive filter circuit is governed at least in part based on the second coefficient set.

13. The method of claim 12 , wherein the method further comprises:

normalizing the second coefficient set such that a variance of a resulting normalized coefficient set is approximately the same as the defined variance, wherein the filter control is the normalized coefficient set.

14. The method of claim 12 , wherein the method further comprises:

applying a data detection algorithm guided by a first filtered output from the first noise predictive filter circuit and a second filtered output from the second noise predictive filter circuit, wherein the data detection algorithm includes a branch metric calculation performed without relying on the variance.

15. The method of claim 14 , wherein the data detection algorithm is a Viterbi data detection algorithm.

16. The method of claim 14 , wherein the method further comprises:

selecting the defined variance is selected such that the branch metric calculation can be done without the first variance and the second variance.

17. The method of claim 14 , wherein the method further comprises:

applying a low density parity check algorithm to the detected output to yield a decoded output.

18. The method of claim 14 , wherein the method further comprises:

updating the first coefficient set to the first noise predictive filter circuit; and

updating the second coefficient set is updated to the second noise predictive filter.

19. A storage device, the storage device comprising:

a storage medium;

a head assembly disposed in relation to the storage medium and operable to provide a sensed signal corresponding to information on the storage medium;

a read channel circuit including:

an analog front end circuit operable to provide an analog signal corresponding to the sensed signal;

an analog to digital converter circuit operable to sample the analog signal to yield a series of digital samples;

an equalizer circuit operable to equalize the digital samples to yield a sample set;

a data detector circuit operable to apply a data detection algorithm to the sample set to yield a detected output, wherein the data detector circuit includes:

a first noise predictive filter circuit, wherein operation of the first noise predictive filter circuit is based at least in part on a first coefficient set;

a second noise predictive filter circuit, wherein operation of the second noise predictive filter circuit is based at least in part on a second coefficient set; and

a forced variance filter coefficient adaptation circuit operable to adapt the first coefficient set and the second coefficient set while constraining at least one of a first variance of the first coefficient set and a second variance of the second coefficient set to a defined variance.

20. The storage device of claim 19 , wherein the storage medium includes both a magnetic storage medium and a solid state memory device.

Assignments (11)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 049248/0558 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047351/0384 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0910 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2012
From: PAN, LU; JEONG, SEONGWOOK; XIA, HAITAO
To: LSI CORPORATION
Reel/Frame 028863/0309 →
Continuity (1)
Related Publication 20140063637A1 · Mar 6, 2014