Semiconductor device and control method of the same
View Patent ↗The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.
1. A semiconductor device comprising:
means for comparing a voltage level at a reference cell data line with a predefined voltage level; and
a first charging means operable to charge the reference cell data line when a voltage level at a reference cell data line is lower than a predefined voltage level during pre-charging the reference cell data line;
a second charging means operable to charge the reference cell data line when a voltage level at a reference cell data line is lower than a predefined voltage level during pre-charging the reference cell data line; and
means for storing data comprising a core cell, wherein the core cell comprises a first bit and a second bit.
2. The semiconductor device of claim 1 , further comprising:
an averaging means coupled to multiple reference cells, wherein the second charging means outputs an output from an average circuit.
3. The semiconductor device of claim 1 , further comprising:
means for sensing after pre-charging of the reference cell data line is finished.
4. The semiconductor device of claim 1 , wherein the core cell is a Silicon Oxide Nitride Oxide Silicon (SONOS) type memory cell.
5. The semiconductor device of claim 2 , wherein the averaging means has a first average circuit outputting to the first current-voltage conversion circuit, and a second average circuit outputting an output thereof to the means for sensing.
6. The semiconductor device of claim 1 , wherein the second charging means comprises a differential circuit to which the voltage level at the reference cell data line and the predefined voltage level are input.