METHOD TO IMPLEMENT A BINARY FLAG IN FLASH MEMORY

1 . A method for changing a state of a binary flag in a flash memory where the flash memory includes memory sections having bits where the bits can only separately be changed from a logical 1 to a logical 0 without erasing the entire memory section, said method comprising:

defining a cell segment in the flash memory section including a predetermined number of bits as the binary flag where each bit is converted to a logical 1 when the memory section is erased;

defining that an even number of logical 1 bits in the flash cell segment is an even parity and an odd number of logical 1 bits in the flash cell segment is an odd parity;

defining whether an even parity is an ON state of the binary flag or an odd parity is an ON state of the binary flag; and

changing the parity of the binary flag by writing one of the bits in the binary flag from a logical 1 to a logical 0 to change the state of the flag.

2 . The method according to claim 1 wherein changing one of the bits in the flash cell segment from a logical 1 bit to a logical 0 bit includes performing a logical shift left.

3 . The method according to claim 1 wherein changing one of the bits in the flash cell segment from a logical 1 bit to a logical 0 bit includes performing a logical shift right.

4 . The method according to claim 1 wherein defining a flash cell segment including a predetermined number of bits includes defining the flash cell segment to include an even number of bits if it is desirable to have a final flag state the same as an initial flag state and an odd number of bits if it is desirable to have a final flag state different than the initial flag state.

5 . The method according to claim 1 further comprising disabling the binary flag from further state changes by setting all of the bits in the cell segment to logical 0s.

6 . The method according to claim 1 wherein the flash memory is a memory in an electronic control unit (ECU) on a vehicle.

7 . A method for changing a state of a binary flag in a flash memory in an electronic control unit (ECU) on a vehicle, where the flash memory includes memory sections having bits where the bits can only separately be changed from a logical 1 to a logical 0 without erasing the entire memory section, said method comprising:

defining a flash cell segment in the memory section including a predetermined number of bits as the binary flag;

defining that an even number of logical 1 bits in the flash cell segment is an even parity and an odd number of logical 1 bits in the flash cell segment is an odd parity;

defining whether an even parity is an ON state of the binary flag or an odd parity is an ON state of the binary flag; and

changing the parity of the binary flag by writing one of the bits in the binary flag from a logical 1 to a logical 0 to change the state of the flag.

8 . The method according to claim 7 wherein changing one of the bits in the flash cell segment from a logical 1 bit to a logical 0 bit includes performing a logical shift left.

9 . The method according to claim 7 wherein changing one of the bits in the flash cell segment from a logical 1 bit to a logical 0 bit includes performing a logical shift right.

10 . The method according to claim 7 wherein defining a flash cell segment including a predetermined number of bits includes defining the flash cell segment to include an even number of bits if it is desirable to have a final flag state the same as an initial flag state and an odd number of bits if it is desirable to have a final flag state different than the initial flag state.

11 . The method according to claim 7 further comprising disabling the binary flag from further state changes by setting all of the bits in the cell segment to logical 0s.

12 . A system for changing a state of a binary flag in a flash memory where the flash memory includes memory sections having bits where the bits can only separately be changed from a logical 1 to a logical 0 without erasing the entire memory section, said system comprising:

means for defining a flash cell segment in the memory section including a predetermined number of bits as the binary flag where each bit is converted to a logical 1 when the memory section is erased;

means for defining that an even number of logical 1 bits in the flash cell segment is an even parity and an odd number of logical 1 bits in the flash cell segment is an odd parity;

means for defining whether an even parity is an ON state of the binary flag or an odd parity is an ON state of the binary flag; and

means for changing the state of the binary flag by writing one of the bits in the flash cell segment from a logical 1 to a logical 0 to change the parity and the state of the flag.

13 . The system according to claim 12 wherein the means for changing one of the bits in the flash cell segment from a logical 1 bit to a logical 0 bit performs a logical shift left.

14 . The system according to claim 12 wherein the means for changing one of the bits in the flash cell segment from a logical 1 bit to a logical 0 bit performs a logical shift right.

15 . The system according to claim 12 wherein the means for defining a flash cell segment including a predetermined number of bits defines the flash cell segment to include an even number of bits if it is desirable to have a final flag state the same as an initial flag state and an odd number of bits if it is desirable to have a final flag state different than the initial flag state.

16 . The system according to claim 12 further comprising means for disabling the binary flag from further state changes by setting all of the bits in the cell segment to logical 0s.

17 . The system according to claim 12 wherein the flash memory is a memory in an electronic control unit (ECU) on a vehicle.