Semiconductor device having latency counter to control output timing of data and data processing system including the same

1. A semiconductor device comprising:

a command decoder generating a first internal command in response to a first internal clock signal; and

a latency counter that includes:

a gate control signal generation unit generating a plurality of output gate signals in response to a second internal clock signal that is different from the first internal clock signal;

a plurality of delay circuits each receiving an associated one of the output gate signals and generating an associated one of a plurality of input gate signals, each of the delay circuits including a first delay element that operates on a first power supply voltage and a second delay element that operates on a second power supply voltage, the first power supply voltage being different from the second power supply voltage; and

a command signal latch unit fetching the first internal command in response to one of the input gate signals and outputting the first internal command as a second internal command in response to one of the output gate signals.

2. The semiconductor device as claimed in claim 1 , wherein each of the first and second internal commands includes an internal read command.

3. The semiconductor device as claimed in claim 1 , further comprising a first clock generation circuit generating the second internal clock signal and including a first circuit portion that operates on the first power supply voltage and a second circuit portion that operates on the second power supply voltage, and wherein the first delay element has a delay time that is substantially equal to a delay time of the first circuit of the first clock generation circuit.

4. The semiconductor device as claimed in claim 2 , wherein the second delay element has a delay time that is substantially equivalent to a delay time of the second circuit of the first clock generation circuit.

5. The semiconductor device as claimed in claim 3 , wherein the first clock generation circuit includes a DLL circuit.

6. The semiconductor device as claimed in claim 1 , wherein the second internal clock signal leads in phase to the first internal clock signal.

7. The semiconductor device as claimed in claim 6 , further comprising:

a clock terminal supplied with an external clock signal,

a first clock generation circuit generating the first internal clock signal in response to the external clock signal, and

a second clock generation circuit generating the second internal clock signal in response to the external clock signal.

8. The semiconductor device as claimed in claim 1 , the first and second delay elements of each of the delay circuits are coupled in series to each other.

9. The semiconductor device as claimed in claim 1 , wherein each of the delay circuits further includes a third delay element operating on the second power supply voltage.

10. The semiconductor device as claimed in claim 9 , wherein the first to third delay elements of each of the delay circuits are coupled in series to each other.

11. The semiconductor device as claimed in claim 1 , further comprising:

a first power supply terminal externally supplied with the first power supply voltage, and

a voltage generation circuit generating the second power supply voltage in response to the first power supply voltage.

12. The semiconductor device as claimed in claim 11 , wherein the voltage generation circuit includes a regulator circuit.

13. The semiconductor device as claimed in claim 1 , wherein the command decoder operates on the second power supply voltage.

14. The semiconductor device as claimed in claim 12 , wherein the first power supply voltage is greater in voltage level than the second power supply voltage.

15. The semiconductor device as claimed in claim 1 , further comprising:

a memory cell array storing data; and

an output unit receiving the data from the memory cell array in response to the second internal command and outputting the data in response to a third internal clock signal.

16. The semiconductor device as claimed in claim 15 , wherein the second and third internal clock signals are substantially equal in phase to each other.

17. A semiconductor device comprising:

a command decoder operating on an internal power supply voltage and generating a first internal command;

a clock generating circuit generating a first internal clock signal and including a first circuit portion that operates on the internal power supply voltage and a second circuit portion that operates on an external power supply voltage; and

a latency counter that includes:

a gate control signal generation unit generating a plurality of output gate signals in response to the first internal clock signal;

a plurality of delay circuits each receiving an associated one of the output gate signals and generating an associated one of a plurality of input gate signals, each of the delay circuits having a delay time that changes in response to variations of both of the internal and external power supply voltages; and

a command signal latch unit fetching the first internal command in response to one of the input gate signals and outputting the first internal command as a second internal command in response to one of the output gate signals.

18. The semiconductor device as claimed in claim 17 , wherein each of the first and second internal commands includes an internal read command.

19. The semiconductor device as claimed in claim 17 , wherein the clock generating circuit includes a DLL circuit.

20. The semiconductor device as claimed in claim 17 , further comprising:

a memory cell array storing data; and

an output unit receiving the data from the memory cell array in response to the second internal command and outputting the data in response to a second internal clock signal.