Semiconductor device including output circuit constituted of plural unit buffer circuits in which impedance thereof are adjustable
View Patent ↗The semiconductor device comprises an output circuit that includes a plurality of unit buffer circuits each of which has an adjustable impedance, a control circuit that selectively activates one or ones of the unit buffer circuits, and an impedance adjustment unit that adjusts the impedances of the unit buffer circuits and includes a power line, a replica circuit, which has a replica impedance that is substantially equal to the adjustable impedance of each of the unit buffer circuits, and a load current generation circuit, which changes current flowing therethrough in accordance with the number of activated the one or ones of the unit buffer circuits. The replica circuit and the load current generation circuit are connected in common to the power line.
1. A semiconductor device comprising:
an output circuit including a plurality of unit buffer circuits, an impedance of each of the unit buffer circuits being adjustable;
a control circuit selectively activating one or ones of the unit buffer circuits; and
an impedance adjustment unit adjusting the impedances of each of the unit buffer circuits, the impedance adjustment unit including a first power line, a replica circuit and a load current generation circuit, the replica circuit and the load current generation circuit being connected in common to the first power line, the replica circuit having an replica impedance that is substantially equal to the impedance of each of the output circuits, the load current generation circuit changing current flowing therethrough in accordance with the number of activated the one or ones of the unit buffer circuits.
2. The semiconductor device as claimed in claim 1 , further comprising a first terminal connected to the replica circuit and configured to be coupled an external resistor having a predetermined resistance value, and wherein
the impedance adjustment unit generates an impedance adjustment signal such that the replica impedance of the replica circuit becomes substantially equal to the resistance value of the external resistor, and the impedance adjustment unit supplies the impedance adjustment signal to the unit buffer circuits to adjust the impedances of the unit buffers.
3. The semiconductor device as claimed in claim 2 , wherein
the replica circuit allows a first current to flow in accordance with the impedance adjustment signal between the first power line and a second power line, the first power line being connected to a power supply, the second power line being connected to the external resistor, and
the load current generation circuit allows a second current whose quantity is substantially equal to a value calculated by subtracting one from the number of activated one or more of the unit buffer circuits and multiplying a resultant value by a quantity of the first current to flow from the first power line to a third power line, the third power line being supplied with substantially the same potential as the second power line.
4. The semiconductor device as claimed in claim 3 , wherein
the load current generation circuit includes a plurality of series circuits, each of the series circuits including a resistor having a first node connected to the third power line, a first transistor connected to a second node of the resistor, and a second transistor connected between the first transistor and the first power line,
the load current generation circuit further includes an operation amplifier that adjusts the first transistor of each of the series circuits by comparing a voltage level of the second node of the resistor of one of the series circuits with a voltage level that appears on the first terminal, and
the load current generation circuit allows the second current to flow to the third power line when the first and second transistors included in at least one of the series circuits are brought into ON state.
5. The semiconductor device as claimed in claim 3 , wherein
the load current generation circuit includes a plurality of load current generation units,
each of the load current generation units includes a resistor having a first node connected to the third power line, a first transistor connected to a second node of the resistor, and a second transistor connected between the first transistor and the first power line,
the load current generation circuit further includes:
a voltage-dividing circuit that divides a voltage level of the first power line to generate a divided voltage; and
a comparator circuit that controls the first transistor of each of the load current generation units by comparing a voltage level of the second node of the resistor of one of the load current generation units with the divided voltage, and
each of the load current generation units allows the second current to flow to the third power line according to the divided voltage when the first and second transistors included therein are brought into ON state.
6. The semiconductor device as claimed in claim 4 , further comprising a mode register indicating the number of the unit buffer circuits to be activated, wherein
the control circuit outputs a setting signal based on an output signal of the mode register, and
the impedance adjustment unit includes a load current selection circuit that selectively brings the second transistor of each of the series circuits into ON state based on the setting signal.
7. The semiconductor device as claimed in claim 6 , further comprising a second terminal, wherein
each of the unit buffer circuits includes a pull-up circuit that drives the second terminal to a voltage level of the first power line and a pull-down circuit that drives the second terminal to a voltage level of the second power line,
the setting signal includes a first setting signal and a second setting signal,
when a read command that instructs the semiconductor device to read a data from an internal circuit and output the data to the second terminal is issued to the semiconductor device, the control circuit activates one of the pull-up circuit and the pull-down circuit included in the selected one or more of the unit buffer circuits in accordance with the first setting signal, thereby driving the second terminal, and
when an On-Die Termination signal that instructs the output circuit to function as a terminating resistor is issued to the semiconductor device, the control circuit activates both the pull-up circuit and the pull-down circuit included in the selected one or more of the unit buffer circuits in accordance with the second setting signal, thereby driving the second terminal.
8. A device comprising:
a first terminal;
a plurality of output buffers coupled in common to the first terminal;
an output control circuit receiving a first control signal and activating one or ones of the output buffers in response to the first control signal; and
an impedance adjustment unit including a replica circuit, a plurality of current generation circuits and a power line, the replica circuit and the current generation circuits being coupled in common to the power line, the impedance adjustment unit adjusting an impedance of each of the output buffers in response to an impedance of the replica circuit, the impedance adjustable circuit further including a current control circuit receiving the first control signal and activating one or ones of the current generation circuits in response to the first control signal.
9. The device as claimed in claim 8 , further comprising a mode resistor circuit storing information that is indicate the number of the one or ones of the output buffers and supplying the first control signal both of the output control circuit and the impedance adjustment unit in response to the information.
10. The device as claimed in claim 8 , wherein the impedance adjustment unit supplies a second control signal to the output control circuit in response to the impedance of the replica circuit, and the output control circuit adjusts the impedance of each of the output buffers in response to the second control signal.
11. The device as claimed in claim 8 , wherein each of the current generation circuits of the impedance adjustment unit is configured to apply a first current thereto, the first current is substantially equal to a current that is applied to the replica circuit of the impedance adjustment circuit.
12. The device as claimed in claim 8 , further comprising a second terminal configured to be coupled to an external resistor that has a first resistance value, and wherein each of the current generation circuits of the impedance adjustment unit includes a second resistor having a second resistive value that is substantially equal to the first resistive value.
13. The device as claimed in claim 12 , wherein the replica circuit is coupled to the second terminal.
14. The device as claimed in claim 12 , wherein each of the current generation circuits includes a transistor coupled between the second resistor and the power line, the transistor of each of the current generation circuits includes a control node coupled to the current control circuit.
15. A system comprising:
a control device; and
a memory device coupled to the control device, the memory device comprising;
a first terminal coupled to the control device;
a plurality of output buffers coupled in common to the first terminal;
an output control circuit receiving a first control signal and activating one or ones of the output buffers in response to the first control signal; and
an impedance adjustment unit including a replica circuit, a plurality of current generation circuits and a power line, the replica circuit and the current generation circuits being coupled in common to the power line, the impedance adjustment unit adjusting an impedance of each of the output buffers in response to an impedance of the replica circuit, the impedance adjustable circuit further including a current control circuit receiving the first control signal and activating one or ones of the current generation circuits in response to the first control signal.
16. The system as claimed in claim 15 , wherein the memory device further comprises a mode resistor circuit storing information that is indicate the number of the one or ones of the output buffers and supplying the first control signal both of the output control circuit and the impedance adjustment unit in response to the information.
17. The system as claimed in claim 15 , wherein the impedance adjustment unit of the memory device supplies a second control signal to the output control circuit in response to the impedance of the replica circuit, and the output control circuit adjusts the impedance of each of the output buffers in response to the second control signal.
18. The system as claimed in claim 15 , wherein each of the current generation circuits of the impedance adjustment unit of the memory device is configured to apply a first current thereto, the first current is substantially equal to a current that is applied to the replica circuit of the impedance adjustment circuit.
19. The system as claimed in claim 15 , wherein the memory device further comprises a second terminal configured to be coupled to an external resistor that has a first resistance value, and each of the current generation circuits of the impedance adjustment unit of the memory device includes a second resistor having a second resistive value that is substantially equal to the first resistive value.
20. The system as claimed in claim 19 , wherein the replica circuit of the adjustment unit of the memory device is coupled to the second terminal.