SEMICONDUCTOR DEVICE INCLUDING DUMMY PILLAR NEAR INTERMEDIATE PORTION OF SEMICONDUCTOR PILLAR GROUP

1 . A semiconductor device comprising:

a semiconductor pillar group comprising a plurality of semiconductor pillars which are formed in a first direction with a space left therebetween;

a dummy pillar disposed near a particular semiconductor pillar in the semiconductor pillar group in a second direction perpendicular to the first direction, the particular semiconductor pillar being any one of the semiconductor pillars which are positioned in an intermediate portion exclusive of both end portions;

gate insulating films which are formed on outer circumferential surfaces of the plurality of semiconductor pillars and one of which is formed on a part of an outer circumferential surface of the dummy pillar; and

gate electrodes which is formed over side faces of the plurality of semiconductor pillars and one of which is formed over a side face of the dummy pillar via the gate insulating films so as to fill gaps between the plurality of semiconductor pillars and a gap between the particular semiconductor pillar and the dummy pillar.

2 . The semiconductor device as claimed in claim 1 , wherein the dummy pillar is disposed at a position extending over an active region and an element isolation region, the dummy pillar comprising a composite pillar into which a dummy silicon pillar and an insulating layer pillar are incorporated.

3 . The semiconductor device as claimed in claim 1 , wherein the particular semiconductor pillar comprises one of the plurality of semiconductor pillars that is located at a central portion of the semiconductor pillar group.

4 . The semiconductor device as claimed in claim 1 , wherein the interval between adjacent semiconductor pillars is double or less the thickness of each gate electrode, the interval between the particular semiconductor pillar and the dummy pillar is double or less the thickness of each gate electrode.

5 . The semiconductor device as claimed in claim 1 , wherein further comprises:

a first insulating film formed on a substrate which is exposed about the respective semiconductor pillars; and

a drain diffused layer formed under the first insulating film, whereby the gate electrode and the drain diffused layer are insulated by the first insulating film.

6 . The semiconductor device as claimed in claim 2 , wherein further comprises:

a mask film disposed on the dummy pillar, the mask film together with the dummy pillar serving as a protrusion portion shoring up a height of the gate electrode;

an interlayer insulating film formed on the mask film;

a gate conductive plug penetrating the interlayer insulating film; and

a gate wire disposed on the interlayer insulating layer, the gate wire being connected via the gate conductive plug to the gate electrode which covers a side surface of the protrusion portion.

7 . The semiconductor device as claimed in claim 6 , wherein the gate conductive plug is disposed at a side of the insulating layer pillar.

8 . The semiconductor device as claimed in claim 1 ,

wherein further comprises source diffused layers formed at upper portions of the plurality of semiconductor pillars,

wherein the gate electrodes have opening portions formed on upper faces of the plurality of semiconductor pillars,

wherein further comprises:

second insulating films formed on internal wall surfaces of the opening portions of the gate electrodes; and

silicon plugs formed in the opening portions of the gate electrodes via the second insulating films so as to be electrically connected to the source diffused layers, whereby the gate electrodes and the silicon plugs are insulated to each other by the second insulating films.

9 . The semiconductor device as claimed in claim 1 , wherein comprises a unit transistor group comprising a plurality of unit transistors corresponding to the plurality of semiconductor pillars, respectively, the unit transistor group constituting a single parallel transistor.

10 . A semiconductor device comprising:

a first semiconductor pillar group comprising first through N-th semiconductor pillars which are formed in a first direction with a space left therebetween, where N represents a positive integer which is not less than three;

a second semiconductor pillar group adjacent to the first semiconductor pillar group, the second semiconductor pillar group comprising (N+1)-th through 2N-th semiconductor pillars which are formed in the first direction with a space left therebetween;

a first dummy pillar disposed near a first particular semiconductor pillar in the first semiconductor pillar group in a second direction perpendicular to the first direction, the first particular semiconductor pillar being any one of the second through the (N−1)-th semiconductor pillars which are positioned in an intermediate portion exclusive of the first and the N-th semiconductor pillars;

a second dumpy pillar disposed near a second particular semiconductor pillar in the second semiconductor pillar group in the second direction at an opposite side of the first dummy pillar, the second particular semiconductor pillar being any one of the (N+2)-th through the (2N−1)-th semiconductor pillars which are positioned in an intermediate portion exclusive to the (N+1)-th and the 2N-th semiconductor pillars;

gate insulating films which are formed on outer circumferential surfaces of the first through the 2N-th semiconductor pillars and two of which are formed on parts of outer circumferential surfaces of the first and the second dummy pillars; and

gate electrodes which are formed over side faces of the first through the 2N-th semiconductor pillars and two of which are formed over side faces of the first and the second dumpy pillars via the gate insulating films so as to fill gaps between the first through the 2N-th semiconductor pillars, a gap between the first particular semiconductor pillar and the first dumpy pillar, and a gap between the second particular semiconductor pillar and the second dummy pillar.

11 . The semiconductor device as claimed in claim 10 , wherein each of the first and the second dummy pillars is disposed at a position extending over an active region and an element isolation region, the first dummy pillar comprising a first composite pillar into which a first dummy silicon pillar and a first insulating layer pillar are incorporated, the second dummy pillar comprising a second composite pillar into which a second dummy silicon pillar and a second insulating layer pillar are incorporated.

12 . The semiconductor device as claimed in claim 10 ,

wherein the first particular semiconductor pillar comprises one of the second through the (N−1)-th semiconductor pillars that is located at a central portion of the first semiconductor pillar group,

wherein the second particular semiconductor pillar comprises one of the (N+2)-th through (2N−1)-th semiconductor pillars that is located at a central portion of the second semiconductor pillar group.

13 . The semiconductor device as claimed in claim 10 , wherein the interval between adjacent semiconductor pillars is double or less the thickness of each gate electrode, the interval between the first particular semiconductor pillar and the first dummy pillar is double or less the thickness of each gate electrode, and the interval between the second particular semiconductor pillar and the second dummy pillar is double or less the thickness of each gate electrode

14 . The semiconductor device as claimed in claim 10 , wherein further comprises:

a first insulating film formed on a substrate which are exposed about the first through the 2N-th respective semiconductor pillars; and

a drain diffused layer formed under the first insulating film, whereby the gate electrodes and the drain diffused layer are insulated by the first insulating film.

15 . The semiconductor device as clamed in claim 11 , wherein further comprises:

mask films disposed on the first and the second dummy pillars, the mask films together with the first and the second dummy pillars serving as first and second protrusion portions shoring up a height of the gate electrodes;

an interlayer insulating film formed on the mask films;

a first gate conductive plug penetrating the interlayer insulating film;

a first gate wire disposed on the interlayer insulating layer, the first gate wire being connected via the first gate conductive plug to the gate electrode which covers a side face of the first protrusion portion;

a second gate conductive plug penetrating the interlayer insulating film; and

a second gate wire disposed on the interlayer insulating layer, the second gate wire being connected via the second gate conductive plug to the gate electrode which covers a side face of the second protrusion portion.

16 . The semiconductor device as claimed in claim 15 , wherein the first gate conductive plug is disposed at a side of the first insulating layer pillar, and the second gate conductive plug is disposed at a side of the second insulating layer pillar.

17 . The semiconductor device as claimed in claim 10 ,

wherein further comprises source diffused layers formed at upper portions of the first through the 2N-th semiconductor pillars,

wherein the gate electrodes have opening portions formed upper faces of the first through the 2N-th semiconductor pillars,

wherein further comprises:

second insulating films formed on internal wall surfaces of the opening portions of the gate electrodes; and

silicon plugs formed in the opening portions of the gate electrodes via the second insulating films so as to be electrically connected to the source diffused layers, whereby the gate electrodes and the silicon plugs are insulated to each other by the second insulating films.

18 . The semiconductor device as claimed in claim 10 , wherein comprises:

a first unit transistor group comprising first through N-th unit transistors corresponding to the first through the N-th semiconductor pillars, respectively; and

a second unit transistor group comprising (N+1)-th through 2N-th unit transistors corresponding to the (N+1)-th through the 2N-th semiconductor pillars, respectively,

wherein the first unit transistor group and the second unit transistor group are connected in series to constitute a single serial/parallel transistor.

19 . A semiconductor device comprising:

a first semiconductor pillar group comprising first through N-th semiconductor pillars which are formed in a first direction with a space left therebetween, where N represents a positive integer which is not less than three;

a second semiconductor pillar group adjacent to the first semiconductor pillar group, the second semiconductor pillar group comprising (N+1)-th through 2N-th semiconductor pillars which are formed in the first direction with a space left therebetween;

a first dummy pillar disposed near a first particular semiconductor pillar in the first semiconductor pillar group in a second direction perpendicular to the first direction, the first particular semiconductor pillar being any one of the second through the (N−1)-th semiconductor pillars which are positioned in an intermediate portion exclusive of the first and the N-th semiconductor pillars;

a second dumpy pillar disposed near a second particular semiconductor pillar in the second semiconductor pillar group in the second direction at an opposite side of the first dummy pillar, the second particular semiconductor pillar being any one of the (N+2)-th through the (2N−1)-th semiconductor pillars which are positioned in an intermediate portion exclusive to the (N+1)-th and the 2N-th semiconductor pillars;

gate insulating films which are formed on outer circumferential surfaces of the first through the 2N-th semiconductor pillars and two of which are formed on parts of outer circumferential surfaces of the first and the second dummy pillars;

first gate electrodes which are formed over side faces of the first through the N-th semiconductor pillars and one of which is formed over a side face of the first dumpy pillar via the gate insulating films so as to fill gaps between the first through the N-th semiconductor pillars and a gap between the first particular semiconductor pillar and the first dumpy pillar; and

second gate electrodes which are formed over side faces of the (N+1)-th through the 2N-th semiconductor pillars and one of which is formed over a side face of the second dumpy pillar via the gate insulating films so as to fill gaps between the (N+1)-th through the 2N-th semiconductor pillars and a gap between the second particular semiconductor pillar and the second dummy pillar,

wherein the interval between the first semiconductor pillar group and the second semiconductor pillar group is more double the thickness of each gate electrode.

20 . The semiconductor device as claimed in claim 19 , wherein each of the first and the second dummy pillars is disposed at a position extending over an active region and an element isolation region, the first dummy pillar comprising a first composite pillar into which a first dummy silicon pillar and a first insulating layer pillar are incorporated, the second dummy pillar comprising a second composite pillar into which a second dummy silicon pillar and a second insulating layer pillar are incorporated.