Semiconductor device including low-K dielectric cap layer for gate electrodes and related methods
View Patent ↗A semiconductor device may include a substrate, source and drain regions in the substrate, a recessed epitaxial channel layer in the substrate between the source and drain regions, and a high-K gate dielectric layer overlying the recessed epitaxial channel layer. The semiconductor device may further include a gate electrode overlying the high-K gate dielectric layer, a dielectric cap layer in contact with top and sidewall portions of the gate electrode, the dielectric cap layer having a lower dielectric constant than the high-K gate dielectric layer, and source and drain contacts coupled to the source and drain regions.
1. A semiconductor device comprising:
a substrate;
source and drain regions in said substrate;
a recessed epitaxial channel layer in said substrate extending laterally above at least some portions of said source and drain regions;
a high-K gate dielectric layer overlying said recessed epitaxial channel layer;
a gate electrode overlying said high-K gate dielectric layer;
a dielectric cap layer in contact with top and sidewall portions of said gate electrode, said dielectric cap layer having a lower dielectric constant than said high-K gate dielectric layer; and
source and drain contacts coupled to said source and drain regions;
wherein the high-K gate dielectric layer terminates below a bottom level of the gate electrode.
2. The semiconductor device of claim 1 wherein said gate electrode comprises an inner metal gate electrode portion and an outer metal barrier portion.
3. The semiconductor device of claim 2 wherein said inner metal gate electrode portion comprises aluminum; and wherein said outer metal barrier portion comprises TaNi.
4. The semiconductor device of claim 2 wherein said gate electrode further comprises a work function layer on said outer metal barrier portion.
5. The semiconductor device of claim 4 wherein said work function layer comprises TiN.
6. The semiconductor device of claim 1 wherein said recessed epitaxial channel layer comprises at least one of silicon and germanium.
7. The semiconductor device of claim 1 wherein said source and drain contacts comprise metal.
8. The semiconductor device of claim 1 further comprising a shallow trench isolation (STI) region in said substrate.
9. The semiconductor device of claim 1 further comprising respective silicide regions between each of said source and drain regions and said source and drain contacts.
10. A semiconductor device comprising:
a substrate;
source and drain regions in said substrate, said source and drain contacts comprising metal;
a recessed epitaxial channel layer in said substrate extending laterally above at least some portions of said source and drain regions;
a high-K gate dielectric layer overlying said recessed epitaxial channel layer;
a gate electrode overlying said high-K gate dielectric layer, said gate electrode comprising an inner metal gate electrode portion and an outer metal barrier portion;
a dielectric cap layer in contact with top and sidewall portions of said outer metal barrier portion, said dielectric cap layer having a lower dielectric constant than said high-K gate dielectric layer; and
source and drain contacts coupled to said source and drain regions;
wherein the high-K gate dielectric layer terminates below a bottom level of the gate electrode.
11. The semiconductor device of claim 10 wherein said inner metal gate electrode portion comprises aluminum; and wherein said outer metal barrier portion comprises TaNi.
12. The semiconductor device of claim 10 wherein said gate electrode further comprises a work function layer on said outer metal barrier portion.
13. The semiconductor device of claim 12 wherein said work function layer comprises TiN.
14. The semiconductor device of claim 10 wherein said recessed epitaxial channel layer comprises at least one of silicon and germanium.
15. The semiconductor device of claim 10 further comprising a shallow trench isolation (STI) region in said substrate.
16. The semiconductor device of claim 10 further comprising respective silicide regions between each of said source and drain regions and said source and drain contacts.