Semiconductor device having plural selection lines selected based on address signal
Disclosed herein is a device that includes: a set of address terminals supplied with a set of address signals, each of the address signals being changed in logic level; memory mats to which address ranges are allocated, respectively, the address ranges being different from each other, each of the memory mats including memory cells; and decoder units each provided correspondingly to corresponding memory mat. Each of the decoder units includes a set of first input nodes and a set of second input nodes, the set of first input nodes of each of the decoder units being coupled to the set of address terminals to receive the set of address signals, the set of second input nodes of each of the decoder units being coupled to receive an associated one of sets of control signals, each of the control signals being fixed in logic level.
1. A device comprising:
a plurality of circuit blocks each including a plurality of selection lines to which respective different addresses are assigned so that respective different address ranges are assigned to the circuit blocks;
a first selection circuit selecting one of the circuit blocks by comparing an address signal with information related to the address ranges of the circuit blocks; and
a second selection circuit selecting at least one of the selection lines included in selected one of the circuit blocks based on the address signal,
wherein the address signal comprising a plurality of address bits,
the first selection circuit selects one of the circuit blocks based on a first portion of the address bits,
the second selection circuit selects at least one of the selection lines based on a second portion of the address bits, and
the first and second portions of the address bits overlap with each other at least in part.
2. The device as claimed in claim 1 , wherein the information includes at least one of an address of a selection line to which a maximum address value is assigned and an address of a selection line to which a minimum address value is assigned among the selection lines included in each of the circuit blocks.
3. The device as claimed in claim 2 , wherein the information includes one of the address of the selection line to which the maximum address value is assigned and the address of the selection line to which the minimum address value is assigned among the selection lines included in each of the plurality of circuit blocks, and does not include the other.
4. The device as claimed in claim 1 , wherein the information is nonvolatile information that is obtained in a fixed manner.
5. The device as claimed in claim 1 , wherein
the address signal is a row address,
the circuit blocks are memory mats each including a plurality of memory cells, and
the selection lines are word lines that select at least one of the memory cells.