IP Library Granted Patent US 8,673,657
Granted Patent B2
US 8,673,657 · App. 13/682,324 · Granted Mar 18, 2014

Semiconductor device including a circuit area and a monitor area having a plurality of monitor layers and method for manufacturing the same

Inventor: Kouichi Nagai (Kawasaki, JP)
Assignee: Fujitsu Semiconductor Limited
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Quick Facts
Patent No.
US 8,673,657
App. No.
13/682,324
Granted
Mar 18, 2014
Kind
B2
Abstract

In a circuit area wherein a semiconductor integrated circuit is to be formed, an isolation insulating film is formed on a surface of a semiconductor substrate, and, at the same time, five isolation insulating films extending in one specific direction are formed within a monitor area at a fixed spacing. Then, a gate insulation film and a gate electrode are formed within the circuit area on the semiconductor substrate, and, at the same time, five gate insulation films and five gate electrodes extending in the same direction as the isolation insulating films are formed within the monitor area at the same spacing as that of the isolation insulating films.

Claims (19)

1. A method for manufacturing a semiconductor device, comprising;

forming a circuit area, a first monitor area, and a second monitor area on a chip which a semiconductor wafer is diced into;

forming a first layer composing a semiconductor integrated circuit within said circuit area, a first monitor layer within said first monitor area, and a second monitor layer within said second monitor area;

forming at least five first monitor patterns of substantially the same shape in the first monitor layer, the at least five first monitor patterns being disposed at a first pitch between each other;

forming at least five second monitor patterns of substantially the same shape in the second monitor layer, the at least five second monitor patterns being disposed at the first pitch between each other;

forming a second layer composing said semiconductor integrated circuit on or above said first layer, a third monitor layer on or above said first monitor layer, and a fourth monitor layer on or above said second monitor layer;

forming at least five third monitor patterns of substantially the same shape in the third monitor layer, the at least five third monitor patterns being disposed at a second pitch between each other; and

forming at least five fourth monitor patterns of substantially the same shape in the fourth monitor layer, the at least five fourth monitor patterns being disposed at the second pitch between each other,

wherein all of the first monitor patterns and the third monitor patterns formed within said first monitor area extend in a first direction, and all of the second monitor patterns and the fourth monitor patterns formed within said second monitor area extend in a second direction perpendicular to the first direction.

2. The method according to claim 1 , wherein

the first layer, the first monitor layer, and the second monitor layer are formed simultaneously, and

the second layer, the third monitor layer, and the fourth monitor layer are formed simultaneously.

3. The method according to claim 2 , wherein

the first monitor patterns and the second monitor patterns are formed simultaneously, and

the third monitor patterns and the fourth monitor patterns are formed simultaneously.

4. The method according to claim 1 , further comprising:

forming a first marker on the first monitor area and a second marker on the second monitor area, wherein

the first marker indicates the first direction in which the first monitor pattern and the third monitor pattern extend, and

the second marker indicates the second direction in which the second monitor pattern and the fourth monitor pattern extend.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR MEMORY SOLUTION LIMITED
Reel/Frame 053195/0249 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2012
From: NAGAI, KOUICHI
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 029334/0150 →
Continuity (3)
Division 11855482 · Sep 14, 2007
Continuation PCTJP2005004692 · Mar 16, 2005
Related Publication 20130078803A1 · Mar 28, 2013