Counter management algorithm systems and methods for high bandwidth systems

1. A method, comprising:

receiving a frame and generating a flow update request based thereon;

processing the flow update request for an individual request for a unique addresses;

queuing the individual request in a high speed memory interface;

reading count data from a counter associated with the individual requests from high speed memory;

monitoring rollover bits for the counter with the individual request added thereto;

combining the individual request with the read count data and placing resultant data on a write queue for low speed memory and writing zero to the high speed memory for the counter when one of the rollover bits is set; and

combining the individual request with the read count data and writing the resultant data back to the high speed memory when the rollover bits are not set.

2. The method of claim 1 , wherein an update to the low speed memory is substantially faster than a rollover time for the counter in the high speed memory thereby allowing statistics to be cached in the high speed memory while updates take place to the low speed memory.

3. The method of claim 1 , wherein the counter in the high speed memory comprises a width of N, N being an integer, and wherein the rollover bits comprise a first rollover bit being a second most significant bit, N−1, of the counter and a second rollover bit being a first most significant bit, N, of the counter.

4. The method of claim 3 , further comprising:

determining the first rollover bit is set;

writing the resultant data to the high speed memory responsive to the write queue for the low speed memory being full;

determining the second rollover bit is set subsequent to the determining the first rollover bit is set; and

placing the resultant data in the write queue in a portion reserved thereby always having space.

5. The method of claim 1 , wherein the rollover bits are maintained as part of the resultant data in the counter in the high speed memory.

6. The method of claim 1 , further comprising:

determining whether to move the counter from the high speed memory to the low speed memory in conjunction with a read of the counter associated with a counter update.

7. The method of claim 1 , wherein the low speed memory comprises Dynamic random-access memory and the high speed memory comprises Static random-access memory.

8. The method of claim 1 , wherein the counter comprises both packet count data and byte count data.

9. The method of claim 1 , further comprising:

compressing the individual request for the unique addresses.

10. A statistics subsystem, comprising:

electrical processing logic configured to:

receive a frame and generating a flow update request based thereon;

process the flow update request for an individual request for a unique addresses;

queue the individual request in a high speed memory interface;

read count data from a counter associated with the individual requests from high speed memory;

monitor rollover bits for the counter with the individual request added thereto;

combine the individual request with the read count data and placing resultant data on a write queue for low speed memory and writing zero to the high speed memory for the counter when one of the rollover bits is set; and

combine the individual request with the read count data and writing the resultant data back to the high speed memory when the rollover bits are not set.

11. The statistics subsystem of claim 10 , wherein an update to the low speed memory is substantially faster than a rollover time for the counter in the high speed memory thereby allowing statistics to be cached in the high speed memory while updates take place to the low speed memory.

12. The statistics subsystem of claim 10 , wherein the counter in the high speed memory comprises a width of N, N being an integer, and wherein the rollover bits comprise a first rollover bit being a second most significant bit, N−1, of the counter and a second rollover bit being a first most significant bit, N, of the counter.

13. The statistics subsystem of claim 12 , wherein the electrical processing logic is further configured to:

determine the first rollover bit is set;

write the resultant data to the high speed memory responsive to the write queue for the low speed memory being full; and

determine the second rollover bit is set subsequent to the determining the first rollover bit is set; and

place the resultant data in the write queue in a portion reserved thereby always having space.

14. The statistics subsystem of claim 10 , wherein the rollover bits are maintained as part of the resultant data in the counter in the high speed memory.

15. The statistics subsystem of claim 10 , wherein the electrical processing logic is further configured to:

determine whether to move the counter from the high speed memory to the low speed memory in conjunction with a read of the counter associated with a counter update.

16. The statistics subsystem of claim 10 , wherein the low speed memory comprises Dynamic random-access memory and the high speed memory comprises Static random-access memory.

17. The statistics subsystem of claim 10 , wherein the counter comprises both packet count data and byte count data.

18. The statistics subsystem of claim 10 , wherein the electrical processing logic is further configured to:

compress the individual request for the unique addresses.

19. A system, comprising:

a network processor providing Ethernet processing of packets;

an offload statistics circuit communicatively coupled to the network processor receiving statistics from the network processor associated with the Ethernet processing of packets;

high speed memory communicatively coupled to the offload statistics circuit for caching of counters of the statistics; and

low speed memory communicatively coupled to the offload statistics circuit for storing the counters from the high speed memory based on detecting a rollover of rollover bits stored in each of the counters when adding the statistics thereto, wherein the counter in the high speed memory comprises a width of N, N being an integer, and wherein the rollover bits comprise a first rollover bit being a second most significant bit, N−1, of the counter and a second rollover bit being a first most significant bit, N, of the counter.

20. The system of claim 19 , wherein an update to the low speed memory is substantially faster than a rollover time for the counter in the high speed memory thereby allowing statistics to be cached in the high speed memory while updates take place to the low speed memory; and

wherein the first rollover bit and the second rollover bit are part of data stored in the counter thereby alleviating a need to maintain a rollover separate from each counter, and wherein a decision to move a counter from the high speed memory to the low speed memory is part of a read and update cycle of the counter in the high speed memory.