High power semiconductor laser diodes
View Patent ↗A high power laser source comprises a bar of laser diodes having a first coefficient of thermal expansion CTE bar on a submount having a second coefficient CTE sub and a cooler having a third coefficient CTE cool . The submount/cooler assembly shows an effective fourth coefficient CTE eff differing from CTE bar . This difference leads to a deformation of the crystal lattice of the lasers' active regions by mechanical stress. CTE eff is selected to be either lower than both CTE bar and CTE cool or is selected to be between CTE bar and CTE cool . The submount may either comprise layers of materials having different CTEs, e.g., a Cu layer of 10-40 μm thickness and a Mo layer of 100-400 μm thickness, or a single material with a varying CTE sub . Both result in a CTE sub varying across the submount's thickness.
1. A method for making a high power laser source of more than one W, said laser source including a bar of laser diodes having a light-emitting active semiconductor region, a cooling element and a submount between said laser bar and said cooling element,
said laser bar having a first coefficient of thermal expansion (CTE bar ),
said submount having a second coefficient of thermal expansion (CTE sub ),
said cooling element having a third coefficient of thermal expansion (CTE cool ), and
a submount/cooler assembly consisting of said submount and said cooling element, said submount/cooler assembly having an effective fourth coefficient of expansion (CTE eff ),
wherein
selecting said fourth coefficient (CTE eff ) different by a predetermined amount from said first coefficient (CTE bar ), CTE eff ≠CTE bar ,
hard soldering said bar of laser diodes to said submount and
hard soldering said submount to said cooling element,
thereby stressing said laser bar's active region to effect a deformation of its semiconductor crystal lattice.
2. The method according to claim 1 , wherein
the predetermined amount of difference between the first coefficient (CTE bar ) and the fourth coefficient (CTE eff ) is selected to be at least 5%.
3. The method according to claim 1 , wherein
the predetermined amount of difference between the first coefficient (CTE bar ) and the fourth coefficient (CTE eff ) is selected to effect a deformation of the crystal lattice of at least about 0.01%.
4. The method according to claim 1 , wherein
said second coefficient (CTE sub ) is selected higher than said first coefficient (CTE bar ) and smaller than or equal to said third coefficient (CTE cool ): CTE sub >CTE bar and CTE sub ≦CTE cool .
5. The method according to claim 1 , wherein
said second coefficient (CTE sub ) is selected smaller than both said first coefficient (CTE bar ) and said third coefficient (CTE cool ): CTE sub <CTE bar and CTE sub <CTE cool .
6. The method according to claim 1 , wherein
the two soldering steps are executed simultaneously.
7. The method according to claim 1 , wherein
the soldering steps are executed at temperatures of about 200-350° C.
8. The method according to claim 1 , wherein
the submount or part of said submount or the assembly consisting of said submount and said cooling element is pre-bent.