SEMICONDUCTOR DEVICE HAVING COMMAND MONITOR CIRCUIT
A semiconductor device includes a plurality of channels, a plurality of command monitor circuits provided corresponding to the plurality of channels, respectively, and a plurality of signal lines coupled in common to the plurality of command monitor circuits. Each of the plurality of command monitor circuits includes a selector configured to receive a plurality of input signals and selectively output a plurality of selected signals among the input signals, based on a first selection information, and an output circuit coupled between the selector and the plurality of signal lines, and configured to output the selected signals to the plurality of signal lines, respectively, based on a second selection information. One of the plurality of command monitor circuits is selected to output the selected signals to the plurality of signal lines while the remaining of the command monitor circuits is non selected, based on the second selection information.
1 . A semiconductor device, comprising:
a plurality of channels;
a plurality of command monitor circuits provided corresponding to the plurality of channels, respectively; and
a plurality of signal lines coupled in common to the plurality of command monitor circuits;
each of the plurality of command monitor circuits comprising:
a selector configured to receive a plurality of input signals and selectively output a plurality of selected signals among the input signals, based on a first selection information; and
an output circuit coupled between the selector and the plurality of signal lines, and configured to output the selected signals to the plurality of signal lines, respectively, based on a second selection information,
wherein one of the plurality of command monitor circuits is selected to output the selected signals to the plurality of signal lines while the remaining of the command monitor circuits is non selected, based on the second selection information.
2 . The semiconductor device as claimed in claim 1 , wherein each of the plurality of command monitor circuits comprises:
an output buffer configured to receive a corresponding one of the selected signals via a corresponding one of the signal lines.
3 . The semiconductor device as claimed in claim 1 , the semiconductor device further comprising:
an output buffer configured to receive the selected signals via the signal lines.
4 . The semiconductor device as claimed in claim 1 , wherein the command monitor circuit further comprises a test register storing the first and second selection information.
5 . The semiconductor device as claimed in claim 1 , wherein the first selection information indicates an information for selecting the plurality of selected signals to be monitored and the second selection information indicates an information for selecting one of the channels to be monitored.
6 . The semiconductor device as claimed in claim 1 , wherein the command monitor circuit receives a signal input to a command decoder.
7 . The semiconductor device as claimed in claim 6 , wherein the signal includes a row address strobe signal.
8 . The semiconductor device as claimed in claim 6 , wherein the signal includes a column address strobe signal.
9 . The semiconductor device as claimed in claim 6 , wherein the signal includes a write enable signal.
10 . The semiconductor device as claimed in claim 6 , wherein the signal includes a chip selection signal.
11 . The semiconductor device as claimed in claim 5 , wherein the command monitor circuit receives a bank address.
12 . The semiconductor device as claimed in claim 5 , wherein the signal includes a clock signal.
13 . The semiconductor device as claimed in claim 5 , wherein the signal includes a data signal.
14 . The semiconductor device as claimed in claim 13 , wherein the signal includes a data strobe signal.
15 . The semiconductor device as claimed in claim 14 , the command monitor circuit further comprising:
a logic circuit receiving the data signal and the data strobe signal,
wherein the selector receives an output of the logic circuit.
16 . A semiconductor chips comprising:
a control chip;
a plurality of semiconductor chips stacked over the control chip, which are configured to be controlled by the control chip, the plurality of semiconductor chips each including a plurality of memory channels and a plurality of command monitor circuits provided corresponding to the memory channels, respectively, the command monitor circuit being configured to output a plurality of monitor signals produced in the associated semiconductor chip when controlled by the control chip in a test mode;
a plurality of signal lines passing through the plurality of semiconductor chips so that the plurality of signal lines are coupled to the command monitor circuits in each of the semiconductor chips;
wherein one of the plurality of command monitor circuits in the plurality of semiconductor chips is selected to output the monitor signals to the plurality of signal lines, based on a selection information.
17 . The semiconductor device according to claim 16 , wherein the selection information includes a channel selection information and a chip selection information.
18 . The semiconductor device according to claim 16 , the semiconductor device further comprising:
an interposer provided such that the control chip is intervened between the semiconductor chips and the interposer, the interposer including a plurality of external terminals so that the signal lines pass through the control chip and are connected to the external terminals.
19 . The semiconductor device according to claim 16 , wherein the command monitor circuit comprises:
a selector configured to select and output selection signals among a plurality of input signals based on a first portion of the selection information;
an output circuit configured to output the selection signals, respectively, based on a second portion of the selection formation.
20 . The semiconductor device according to claim 16 , the command monitor circuit further comprising
a test register storing the selection information.