IP Library Granted Patent US 9,003,263
Granted Patent B2
US 9,003,263 · App. 13/742,340 · Granted Apr 7, 2015

Encoder and decoder generation by state-splitting of directed graph

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Quick Facts
Patent No.
US 9,003,263
App. No.
13/742,340
Granted
Apr 7, 2015
Kind
B2
Abstract

A method of generating a hardware encoder includes generating a first directed graph characterizing a constraint set for a constrained system, identifying a scaling factor for an approximate eigenvector for the first directed graph, applying the scaling factor to the approximate eigenvector for the first directed graph to yield a scaled approximate eigenvector, partitioning arcs between each pair of states in the first directed graph, performing a state splitting operation on the first directed graph according to the partitioning of the arcs to yield a second directed graph, and generating the hardware encoder based on the second directed graph.

Claims (33)

1. A method of generating an encoder comprising:

generating a first directed graph characterizing a constraint set for a constrained system;

identifying a scaling factor for an approximate eigenvector for the first directed graph;

applying the scaling factor to the approximate eigenvector for the first directed graph to yield a scaled approximate eigenvector;

partitioning arcs between each pair of states in the first directed graph;

performing a state splitting operation on the first directed graph according to the partitioning of the arcs to yield a second directed graph; and

generating the encoder based on the second directed graph, wherein the encoder comprises a hardware encoder.

2. The method of claim 1 , wherein the second directed graph contains only single branches in each state.

3. The method of claim 1 , wherein identifying the scaling factor comprises identifying the scaling factor such that for every starting state in the first directed graph, a sum over all follower states of a product of a total number of edges involved in a partition of arcs from the starting state to a follower state by a component of the scaled approximate eigenvector corresponding to the follower state, is greater than or equal to two raised to a power of a block length of the encoder, multiplied by the scaled approximate eigenvector coordinate for the starting state.

4. The method of claim 3 , wherein identifying the scaling factor further comprises beginning with an integer scaling factor of one and incrementing the scaling factor by ones until the greater than or equal to condition is satisfied.

5. The method of claim 1 , wherein a connectivity matrix for the first directed graph, multiplied by the scaled approximate eigenvector, is greater than a vector of real numbers scaled by the scaling factor plus two raised to a power of a block length of the encoder multiplied by the scaled approximate eigenvector.

6. The method of claim 1 , wherein partitioning the arcs comprises partitioning the arcs into sets of a cardinality of a smallest integer not smaller than two raised to a power of a block length of the encoder divided by a scaled eigenvector coordinate of a follower state.

7. The method of claim 1 , wherein the method is at least in part performed by a processor executing instructions.

8. The method of claim 1 , wherein the method is at least in part performed by an integrated circuit.

9. The method of claim 1 , further comprising including the encoder in a storage system to encode data prior to storage in the storage system.

10. The method of claim 1 , further comprising generating a hardware decoder based on the second directed graph.

11. The method of claim 10 , further comprising incorporating the hardware encoder and the hardware decoder in a storage system with a storage medium between the hardware encoder and the hardware decoder.

12. The method of claim 1 , wherein the encoder is designed in a single state-splitting operation.

13. The method of claim 12 , wherein an approximate eigenvector for the first directed graph is scaled before the single state-splitting operation.

14. The method of claim 12 , wherein the single state-splitting operation comprises partitioning arcs between starting states and follower states in the first directed graph into sets of a cardinality of a smallest integer not smaller than two raised to a power of a block length of the encoder divided by a scaled eigenvector coordinate of the follower state.

15. A system for generating an encoder comprising:

a tangible computer readable medium, the computer readable medium including instructions executable by a processor to:

generate a first directed graph characterizing a constraint set for a constrained system;

identify a scaling factor for an approximate eigenvector for the first directed graph;

apply the scaling factor to the approximate eigenvector for the first directed graph to yield a scaled approximate eigenvector;

partition arcs between each pair of states in the first directed graph;

perform a state splitting operation on the first directed graph according to the partitioning of the arcs to yield a second directed graph; and

generate the encoder based on the second directed graph.

16. The system of claim 15 , wherein the second directed graph contains only single branches in each state.

17. The system of claim 15 , wherein the instructions to identify the scaling factor comprise instructions to identify the scaling factor such that for every starting state in the first directed graph, a sum over all follower states of a product of a total number of edges involved in a partition of arcs from the starting state to a follower state by a component of the scaled approximate eigenvector corresponding to the follower state, is greater than or equal to two raised to a power of a block length of the encoder, multiplied by the scaled approximate eigenvector coordinate for the starting state.

18. The system of claim 15 , wherein the instructions to identify the scaling factor comprise instructions to begin with an integer scaling factor of one and to increment the scaling factor by ones until the greater than or equal to condition is satisfied.

19. The system of claim 15 , wherein a connectivity matrix for the first directed graph, multiplied by the scaled approximate eigenvector, is greater than a vector of real numbers scaled by the scaling factor plus two raised to a power of a block length of the encoder multiplied by the scaled approximate eigenvector.

20. The system of claim 15 , wherein the instructions to partition the arcs comprise instructions to partition the arcs into sets of a cardinality of a smallest integer not smaller than two raised to a power of a block length of the encoder divided by a scaled eigenvector coordinate of a follower state.

Assignments (10)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2013
From: KARABED, RAZMIK; YANG, SHAOHUA; CHANG, WU; KRACHKOVSKY, VICTOR
To: LSI CORPORATION
Reel/Frame 029803/0723 →