Semiconductor device comprising capacitor and method of fabricating the same
A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface formed on a major surface of a semiconductor substrate to extend from a memory cell region to a peripheral circuit region thereof. A capacitor lower electrode is formed in the memory cell region to upwardly extend beyond the upper surface of the insulating film on the major surface of the semiconductor substrate. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface. The upper surface of the insulating film is located between the top and bottom surfaces of the capacitor lower electrode part.
1. A semiconductor memory device having a capacitor comprising:
a semiconductor substrate having a main surface;
a transistor formed on the main surface of the semiconductor substrate, the transistor having a gate electrode, a source region, and a drain region;
a first insulator layer formed on the main surface so as to cover the transistor; a conductor plug electrically connected to the source region or the drain region of the transistor, the conductor plug formed in the first insulator layer;
a second insulator layer formed on the first insulator layer, the second insulator layer containing nitrogen;
a third insulator layer formed on an upper surface of the second insulator layer;
a fourth insulator layer formed on an upper surface of the third insulator layer; and
a capacitor lower electrode formed on an inside wall of an opening formed in the second insulator layer, the third insulator layer and the fourth insulator layer, the capacitor lower electrode contacting the conductor plug;
wherein the opening has a first portion defined by the second insulator layer, a second portion defined by the third insulator layer, and a third portion defined by the fourth insulator layer, and
wherein an opening width of the second portion is larger than an opening width of the first portion, and the opening width of the second portion is larger than an opening width of the third portion.
2. The semiconductor memory device having a capacitor according to claim 1 , wherein the second insulator layer comprises silicon nitride.
3. The semiconductor memory device having a capacitor according to claim 1 , further comprising:
a dielectric film formed on the capacitor lower electrode inside the opening; and
a capacitor upper electrode formed on the dielectric film so as to face toward the capacitor lower electrode via the dielectric film inside the opening.
4. The semiconductor memory device having a capacitor according to claim 1 , wherein the capacitor lower electrode is formed without contacting an upper surface of the fourth insulator layer.
5. The semiconductor memory device having a capacitor according to claim 1 , wherein the third insulator layer is in direct contact with the second insulator layer.
6. The semiconductor memory device having a capacitor according to claim 1 , wherein the fourth insulator layer is in direct contact with the third insulator layer.
7. The semiconductor memory device having a capacitor according to claim 1 , wherein an etching rate of the fourth insulator layer is different from an etching rate of the third insulator layer.
8. The semiconductor memory device having a capacitor according to claim 1 , wherein an impurity concentration in the third insulator layer is different from an impurity concentration in the fourth insulator layer.
9. The semiconductor memory device having a capacitor according to claim 1 , further comprising: a bit line formed in the first insulator layer, wherein the bit line is electrically connected to one of the source region and the drain region.
10. The semiconductor memory device having a capacitor according to claim 9 , wherein an upper surface of the conductor plug is located at a higher position than an upper surface of the bit line.