MOS transistor, manufacturing method thereof, and semiconductor device

1. A method of manufacturing a MOS transistor, comprising:

forming a gate electrode over a silicon substrate in a device region defined by a device isolation region in the silicon substrate;

ion-implanting first conductivity-type impurities in the silicon substrate in the device region to form a first conductivity-type source extension region and a first conductivity-type drain extension region on a first side and a second side of a channel region provided directly below the gate electrode, respectively, the first conductivity-type corresponding to n-type or p-type;

forming a first offset sidewall spacer and a second offset sidewall spacer on a first sidewall and a second sidewall of the gate electrode, respectively, the first sidewall of the gate electrode being located on a first side of the channel region and the second sidewall of the gate electrode being located on a second side of the channel region;

ion-implanting first conductivity-type impurities in the silicon substrate using the gate electrode and the first and second offset sidewall spacers as a mask to form a first conductivity-type source region and a first conductivity-type drain region on the first side and the second side of the channel region, respectively, such that the first conductivity-type source region is apart from the channel region and overlaps a part of the source extension region and that the first-conductivity-type drain region is apart from the channel region and overlaps a part of the drain extension region;

forming a stress layer over the silicon substrate, covering the first offset sidewall spacer, the gate electrode, and the second offset sidewall spacer, the stress layer accumulating a first stress corresponding to one of a tensile stress and a compressive stress;

forming a protection layer over the silicon substrate covering the stress layer;

performing chemical mechanical polishing on the protection layer to expose a part of the stress layer covering the first and second offset sidewall spacers and the gate electrode;

patterning by etching the exposed part of the stress layer to separate the stress layer into a first stress layer located on the first side of the channel region and extending along the first offset sidewall spacer and a second stress layer located on the second side of the channel region and extending along the second offset sidewall spacer, the first stress layer and the second stress layer accumulating the first stress, and to expose top faces of the first and second offset sidewall spacers; and

removing by etching the first and second offset sidewall spacers from the top faces thereof to produce a first gap between the first sidewall of the gate electrode and a first extending part of the first stress layer arising upward from the silicon substrate along the first sidewall of the gate electrode, and a second gap between the second sidewall of the gate electrode and a second extending part of the second stress layer arising upward from the silicon substrate along the second sidewall of the gate electrode,

said first stress being the tensile stress if the first conductivity type is the n-type, and said first stress being the compressive stress if the first conductivity type is the p-type.

2. The manufacturing method according to claim 1 , wherein

the removing by etching the first and second offset sidewall spacers from the top faces thereof allows a first residual of the first offset sidewall spacer and a second residual of the second offset sidewall spacer to remain in the first gap and the second gap, respectively, as long as a height of the first residual and a height of the second residual from the silicon substrate are at or less than 40% of a height of the gate electrode.

3. The manufacturing method according to claim 1 , wherein each of the first and second offset sidewall spacers has a first width in a direction of a gate length at a bottom contacting the silicon substrate and a second width smaller than the first width, the second width decreasing as the offset sidewall spacer is apart from the silicon substrate.

4. The manufacturing method according to claim 1 , wherein the removing by etching the first and second offset sidewall spacers from the top faces thereof etches the protection layer concurrently.

5. The manufacturing method according to claim 1 , further comprising:

after producing the first gap and the second gap, forming an interlayer dielectric film over the silicon substrate by a plasma CVD method under a condition so as not to accumulate a substantive stress therein.

6. The manufacturing method according to claim 5 , wherein the interlayer dielectric film is formed so as to cover the first gap and the second gap at top of the first extending part of the first stress layer and top of the second extending part of the second stress layer to maintain the first gap and the second gap under the interlayer dielectric film.

7. The manufacturing method according to claim 5 , wherein the interlayer dielectric film is formed so as to fill the first gap and the second gap.

8. The manufacturing method according to claim 1 , further comprising:

after producing the first gap and the second gap, forming an insulating layer with a uniform thickness over the silicon substrate so as to cover the first gap and the second gap at top of the first extending part of the first stress layer and top of the second extending part of the second stress layer to maintain the first gap and the second gap under the interlayer dielectric film.