Manufacture method of a high voltage MOS semiconductor device
A semiconductor device has: a low concentration drain region creeping under a gate electrode of a MIS type transistor; a high concentration drain region having an impurity concentration higher than the low concentration drain region and formed in the low concentration drain region spaced apart from the gate electrode; and an opposite conductivity type region of a conductivity type opposite to the drain region formed in the low concentration drain region on a surface area between the high concentration drain region and the gate electrode, the opposite conductivity type region and low concentration drain region forming a pn junction.
1. A semiconductor device manufacture method comprising:
preparing a semiconductor substrate having a first region of a first conductivity type;
forming a first drain region of a second conductivity type opposite to said first conductivity type in said first region;
forming a gate insulating film on said first region and said first drain region;
forming a gate electrode on said first gate insulating film, said gate electrode having an overlap with both said first region and said first drain region;
forming an opposite conductivity type region of said first conductivity type by implanting impurities to determine said first conductivity type into a surface layer of said first drain region;
forming an insulating film above said first drain region, said insulating film covering a side wall of said gate electrode on a side of said first drain region and extending to a partial area above said opposite conductivity type region;
forming a second drain region of said second conductivity type having an impurity concentration higher than an impurity concentration of said first drain region, by implanting impurities for determining said second conductivity into said opposite conductivity type region and an underlying region of said first drain region; and
forming a source region of said second conductivity type in said first region on a first end of said first drain region opposite to said gate electrode.
2. The semiconductor device manufacture method according to claim 1 , further comprising:
silicidating a surface layer of said second drain region.
3. The semiconductor device manufacture method according to claim 1 , wherein:
an impurity concentration of said opposite conductivity region is higher than said impurity concentration of said first drain region, and lower than said impurity concentration of said second drain region.
4. The semiconductor device manufacture method according to claim 1 , wherein:
said first end is located under said gate electrode; and
said opposite conductivity type region including a second end which is opposite to said source region and which is located under said gate electrode.
5. The semiconductor device manufacture method according to claim 4 , wherein:
said second end is positioned nearer to a side of said second drain region than said first end.
6. The semiconductor manufacture method according to claim 1 , wherein
said first conductivity type is a p-type and said second conductivity type is an n-type.
7. The semiconductor device manufacture method according to claim 1 , further comprising:
forming third drain region of said second conductivity type between said first drain region and said second drain region.
8. The semiconductor device manufacture method according to claim 7 , wherein:
an impurity concentration of said third drain region is higher than said impurity concentration of said opposite conductivity type region and lower than
said impurity concentration of said second drain region.