SEMICONDUCTOR DEVICE HAVING COMPENSATION CAPACITORS FOR STABILIZING OPERATION VOLTAGE
Disclosed herein is a device that includes first and second memory cell arrays each including a plurality of memory cells, a first power supply line supplying a first voltage to the first memory cell array, a second power supply line supplying the first voltage to the second memory cell array, and a first capacitive element. The first capacitive element is electrically connected to the first power supply line and is electrically disconnected from the second power supply line when the first memory cell array is activated and the second memory cell array is deactivated. The first capacitive element is electrically connected to the second power supply line and is electrically disconnected from the first power supply line when the second memory cell array is activated and the first memory cell array is deactivated.
1 . A device comprising:
first and second memory cell arrays each including a plurality of memory cells;
a first power supply line supplying a first voltage to the first memory cell array;
a second power supply line supplying the first voltage to the second memory cell array; and
a first capacitive element, wherein
the first capacitive element is electrically connected to the first power supply line and is electrically disconnected from the second power supply line when the first memory cell array is activated and the second memory cell array is deactivated, and
the first capacitive element is electrically connected to the second power supply line and is electrically disconnected from the first power supply line when the second memory cell array is activated and the first memory cell array is deactivated.
2 . The device as claimed in claim 1 , further comprising:
a first switch element connected between the first capacitive element and the first power supply line;
a second switch element connected between the first capacitive element and the second power supply line; and
a capacitance control circuit controlling the first and second switch elements,
wherein the capacitance control circuit brings the first switch element into an ON state when the first memory cell array is activated, brings the second switch element into an ON state when the second memory cell array is activated, brings the first switch element into an OFF state when the second memory cell array is activated and the first memory cell array is deactivated, and brings the second switch element into an OFF state when the first memory cell array is activated and the second memory cell array is deactivated.
3 . The device as claimed in claim 1 , further comprising:
a first power supply generation circuit supplying the first voltage to the first power supply line; and
a second power supply generation circuit supplying the first voltage to the second power supply line, wherein
the first power supply generation circuit is activated when the first memory cell array is activated, and
the second power supply generation circuit is activated when the second memory cell array is activated.
4 . The device as claimed in claim 1 , further comprising:
a third memory cell array including a plurality of memory cells;
a third power supply line supplying the first voltage to the third memory cell array; and
a second capacitive element, wherein
the second capacitive element is electrically connected to the second power supply line when the second memory cell array is activated, and
the second capacitive element is electrically connected to the third power supply line when the third memory cell array is activated.
5 . The device as claimed in claim 4 , wherein the first capacitive element is electrically connected to the third power supply line when the third memory cell array is activated.
6 . The device as claimed in claim 1 , wherein the first capacitive element is electrically connected to the first and second power supply lines when neither of the first and second memory cell arrays is activated.
7 . The device as claimed in claim 1 , wherein the first capacitive element is electrically disconnected from the first and second power supply lines when neither of the first and second memory cell arrays is activated.
8 . The device as claimed in claim 7 , further comprising:
a peripheral circuit allocated for the first and second memory cell arrays in common; and
a fourth power supply line supplying a second voltage to the peripheral circuit,
wherein the first capacitive element is electrically connected to the fourth power supply line when neither of the first and second memory cell arrays is activated.
9 . The device as claimed in claim 1 , further comprising first and second memory banks selected according to a bank address signal, the first and second memory banks including the first and second memory cell arrays, respectively.
10 . The device as claimed in claim 1 , wherein
each of the first and second memory cell arrays includes a plurality of word lines and a plurality of bit lines that are connected to the plurality of memory cells, respectively, and a plurality of sense amplifier circuits that are connected to the plurality of bit lines, respectively, and
the first power supply line is connected to the sense amplifier circuits included in the first memory cell array, and
the second power supply line is connected to the sense amplifier circuits included in the second memory cell array.
11 . A device comprising:
first and second memory cell arrays each including a plurality of memory cells and a plurality of sense amplifier circuits that amplify data read from the memory cells, respectively;
a first power supply generation circuit arranged in a first circuit area between the first and second memory cell arrays and supplying a first voltage to the sense amplifier circuits of the first memory cell array via a first power supply line;
a second power supply generation circuit arranged in the first circuit area and supplying the first voltage to the sense amplifier circuits of the second memory cell array via a second power supply line;
a first capacitive element arranged in the first circuit area;
a first switch element connected between the first capacitive element and the first power supply line;
a second switch element connected between the first capacitive element and the second power supply line; and
a capacitance control circuit controlling the first and second switch elements, the capacitance control circuit being configured to bring the first switch element into an ON state and the second switch element into an OFF state when the first memory cell array is activated and the second memory cell array is deactivated, and bring the second switch element into an ON state and the first switch element into an OFF state when the second memory cell array is activated and the first memory cell array is deactivated.
12 . The device as claimed in claim 11 , further comprising:
a third memory cell array including a plurality of memory cells and a plurality of sense amplifier circuits that amplifies data read from the plurality of memory cells, the first, second and third memory cell arrays being nonexclusively activated;
a third power supply generation circuit arranged in a second circuit area and supplying the first voltage to the sense amplifier circuits of the third memory cell array via a third power supply line; and
a third switch element connected between the first capacitive element and the third power supply line, wherein
the third memory cell array is arranged between the second memory cell array and the second circuit area, and
the capacitance control circuit brings the third switch element into an ON when the third memory cell array is activated.
13 . The device as claimed in claim 12 , further comprising:
a second capacitive element arranged in the second circuit area;
a fourth switch element connected between the second capacitive element and the second power supply line; and
a fifth switch element connected between the second capacitive element and the third power supply line,
wherein the capacitance control circuit brings the fourth switch element into an ON state when the second memory cell array is activated, and brings the fifth switch element into an ON state when the third memory cell array is activated.
14 . The device as claimed in claim 11 , further comprising:
a third memory cell array including a plurality of memory cells and a plurality of sense amplifier circuits that amplifies data read from the plurality of memory cells, the first, second and third memory cell arrays being nonexclusively activated;
a third power supply generation circuit arranged in a second circuit area and supplying the first voltage to the sense amplifier circuits of the third memory cell array via a third power supply line;
a second capacitive element arranged in the second circuit area;
a third capacitive element arranged in a third circuit area;
a fifth switch element connected between the second capacitive element and the third power supply line;
a sixth switch element connected between the third capacitive element and the second power supply line; and
a seventh switch element connected between the third capacitive element and the third power supply line, wherein
the third circuit area is arranged between the second memory cell array and the third memory cell array,
the third memory cell array is arranged between the second circuit area and the third circuit area, and
the capacitance control circuit brings the sixth switch element into an ON state when the second memory cell array is activated, and brings the fifth and seventh switch elements into an ON state when the third memory cell array is activated.
15 . The device as claimed in claim 11 , further comprising:
a peripheral circuit allocated for the first and second memory cell arrays in common; and
a fourth power supply line supplying a second voltage to the peripheral circuit,
wherein the first capacitive element is electrically connected to the fourth power supply line when neither of the first and second memory cell arrays is activated.
16 . A device comprising:
a first sense amplifier array for a first memory cell array;
a second sense amplifier array for a second memory cell array;
a first power line conveying a first power voltage to the first sense amplifier array;
a second power line conveying a second power voltage to the second sense amplifier array, the second power voltage being substantially equal to the first power voltage;
a common capacitor;
a first switch connected between the first power line and the common capacitor, the first switch being configured to be one of conductive and non-conductive states in response to a first control signal; and
a second switch connected between the second power line and the common capacitor, the second switch being configured to be one of conductive and non-conductive states in response to a second control signal.
17 . The device as claimed in claim 16 , further comprising a first individual capacitor connected to the first power line and a second individual capacitor connected to the second power line.
18 . The device as claimed in claim 16 , further comprising a first power circuit coupled to the first power line to supply the first power voltage thereto, and a second power supply circuit coupled to the second power line to supply the second power voltage thereto.
19 . The device as claimed in claim 16 , wherein the first control signal takes an active level to render the first switch conductive when the first sense amplifier array is activated, and the second signal takes an active level to render the second switch conductive when the second sense amplifier array is activated.
20 . The device as claimed in claim 18 ,
wherein the first power circuit supplies the first power voltage to the first power line with a first driving ability when the first sense amplifier array is deactivated and with a second driving ability when the first sense amplifier array is activated, the first driving ability being less than the second driving ability;
wherein the second power circuit supplies the second power voltage to the second power line with a third driving ability when the second sense amplifier array is deactivated and with a fourth driving ability when the second sense amplifier array is activated, the third driving ability being less than the fourth driving ability; and
wherein the first control signal takes an active level to render the first switch conductive when the first sense amplifier array is activated, and the second signal takes an active level to render the second switch conductive when the second sense amplifier array is activated.