IP Library Granted Patent US 9,331,180
Granted Patent B2
US 9,331,180 · App. 13/786,252 · Granted May 3, 2016

Semiconductor device and method for fabricating thereof

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Quick Facts
Patent No.
US 9,331,180
App. No.
13/786,252
Granted
May 3, 2016
Kind
B2
Abstract

A silicon nitride film, which is a second hard mask, is dry etched to be removed completely. The silicon nitride film, which is formed on a sidewall of a silicon nitride film used as a first hard mask, has a relatively low etching rate. Therefore, if the silicon nitride film is continued etching until the corresponding portion thereof is removed, polysilicon is etched in a direction of depth in trench shape. Then, floating gates in adjacent cells are separated and a step portion of the polysilicon is formed. Consequently, a remaining portion of the silicon nitride film used as the first hard mask is removed, an ONO film is laminated on a whole surface of the poly silicon having the step portion on an edge that has been etched, and then, a polysilicon for a control gate is laminated on the ONO film.

Claims (9)

1. A method of fabricating a semiconductor device, comprising:

forming a first mask having a first window having a size W 1 on a conductive film that defines a floating gate of the semiconductor;

etching a part of the conductive film in a thickness direction thereof from the first window of the first mask;

forming a second mask having a second window that has a size W 2 (<W 1 ) on the conductive film that is concentric with the first window; and

forming a step on a sidewall of the conductive film wherein the first and second masks are photoresist masks.

2. The method as claimed in claim 1 , wherein the floating gate comprises one of polysilicon and amorphous silicon.

3. The method as claimed in claim 1 , wherein the floating gate is doped with phosphorus.

4. The method as claimed in claim 1 , wherein sidewalls of the floating gate have a plurality of steps on which a dielectric film is provided.

5. The method as claimed in claim 4 , wherein the steps are provided at intervals approximately equal to h/(n+1) where n is the number of steps and h is the height of the sidewalls of the floating gate.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →