Digitization and transport of return paths employing different frequency spectrums

1. A return path transmitter, comprising:

a radio frequency (RF) interface comprising RF inputs;

a first RF input received through the RF interface, the first RF input configured to receive one of a first RF return path electrical signal within a 5 MHz to 42 MHz frequency spectrum and a second RF return path electrical signal within a 5 MHz to 85 MHz frequency spectrum;

a second optional RF input received through the RF interface, the second optional RF input configured to receive a third RF return path electrical signal within a 5 MHz to 42 MHz frequency spectrum;

the RF interface further comprising circuitry configured to perform RF signal conditioning and digitize the RF inputs to present a digitized return path data stream; and

digital circuitry comprising a digital filter and processing logic, wherein the digital filter is configured to filter digitized return path channels received from the RF interface, the digital filter filtering the digitized return path channels by one of a first digital filtering function and a second digital filtering function, thereby producing filtered digital return path signals for transmission.

2. The transmitter of claim 1 , wherein the circuitry configured to perform the RF signal conditioning comprises a low pass filter to attenuate frequencies above 85 MHz.

3. The transmitter of claim 1 , wherein the first digital filtering function is configured to attenuate frequencies above 42 MHz.

4. The transmitter of claim 3 , wherein the first digital filtering function is further configured to perform decimation by one half.

5. The transmitter of claim 1 , wherein the second digital filtering function is configured to attenuate frequencies above 85 MHz.

6. The transmitter of claim 1 , wherein the digital circuitry is implemented in a field programmable gate array (FPGA) using FPGA images.

7. The transmitter of claim 6 , wherein different FPGA images are used to implement each one of the first digital filtering function attenuating frequencies above 42 MHz and perform decimation of one half and the second digital filtering function attenuating frequencies above 85 MHz.

8. A system, comprising:

a radio frequency (RF) interface comprising RF inputs each configured to receive an RF return path electrical signal, wherein the RF return path electrical signal is one of a legacy RF return path electrical signal and an extended RF return path electrical signal;

the RF interface further comprising analog to digital converters configured to convert the RF inputs to digitized return path channels;

the RF interface further comprising a multiplexer configured to multiplex the digitized return path channels;

digital circuitry comprising a digital filter, wherein the digital filter is configured to filter the digitized return path channels by different filtering functions;

the digital circuitry further comprising processing logic and a digital output interface, wherein the processing logic is configured to process the digitized return path channels to produce a digital output to the digital output interface; and

an optical interface configured to generate an optical output from the digital output interface of the digital circuitry.

9. The system of claim 8 , wherein the legacy RF return path electrical signal is in the 5 MHz to 42 MHz frequency spectrum.

10. The system of claim 8 , wherein the extended RF return path electrical signal is in the 5 MHz to 85 MHz frequency spectrum.

11. The system of claim 8 , wherein a double data rate (DDR) interface is used to connect the RF interface to the digital circuitry and the digital circuitry to the optical interface.

12. The system of claim 8 , wherein the digital circuitry is implemented in a field programmable gate array (FPGA) using FPGA images.

13. The system of claim 12 , wherein different FPGA images are used to implement different filtering functions.

14. The system of claim 8 , wherein the processing logic configured to process the digitized return path channels and the digital output interface are the same.

15. The system of claim 8 , wherein the processing logic and the digital output operate with a substantially identical clock rate.

16. The system of claim 8 , wherein one digitized return path channel is used for the legacy RF return path electrical signal and two digitized return path channels are used for the extended RF return path electrical signal.

17. A method, comprising:

receiving radio frequency (RF) inputs each configured to receive an RF return path electrical signal, wherein the RF return path electrical signal comprises one of a legacy RF return path electrical signal and an extended RF return path electrical signal;

digitally converting the RF inputs to digitized return channels;

digitally filtering one digital return path channel used for the legacy RF return path electrical signal by a first filtering function and digitally filtering two digital return path channels used for the extended RF return path electrical signal by a second filtering function;

processing the digitized return path channels to produce a digital output; and

optically generating an optical output from the digital output.

18. The method of claim 17 , wherein the digitally filtering is performed by a field programmable gate array (FPGA) using FPGA images.

19. The method of claim 18 , wherein different FPGA images are used to implement each of the first filtering function and the second filtering function.