Biased bang-bang phase detector for clock and data recovery
An apparatus includes a plurality of phase detector circuits and a summing circuit. Each of the plurality of phase detector circuits may be configured to generate a phase up signal and a phase down signal in response to a respective pair of data samples and intervening transition sample. The summing circuit may be configured to generate an adjustment signal in response to the phase up and phase down signals of the plurality of phase detector circuits. A sum of the phase up signals and a sum of the phase down signals are weighted to provide a bias to a phase adjustment.
1. An apparatus comprising:
a plurality of phase detector circuits each configured to generate a phase up signal and a phase down signal in response to a respective pair of data samples and intervening transition samples; and
a summing circuit configured to generate an adjustment signal in response to said phase up and phase down signals of said plurality of phase detector circuits, wherein a sum of said phase up signals and a sum of said phase down signals are weighted to provide a bias to a phase adjustment, wherein said adjustment signal is based on a difference between said sum of said phase up signals weighted by a first control parameter and said sum of said phase down signals weighted by a second control parameter.
2. The apparatus according to claim 1 , wherein said bias is set based on a target bit error rate of an inner eye.
3. The apparatus according to claim 1 , wherein said phase up signals are weighted by said first control parameter, said phase down signals are weighted by said second control parameter, and a ratio of said first control parameter and said second control parameter is set based on a target bit error rate of an inner eye.
4. The apparatus according to claim 1 , further comprising:
a loop filter and clock generation circuit configured to adjust a phase of a transition sampling clock according to said adjustment signal.
5. The apparatus according to claim 1 , further comprising:
at least one data detector configured to generate said data samples in response to a received signal and a data sampling clock; and
at least one transition detector configured to generate said intervening transition samples in response to said received signal and a transition sampling clock, wherein a phase of said transition sampling clock is adjusted according to said adjustment signal.
6. The apparatus according to claim 1 , further comprising:
at least one data detector configured to generate said data samples in response to a received signal and a data sampling clock;
at least one transition detector configured to generate said intervening transition samples in response to said received signal and a transition sampling clock; and
a loop filter and clock generation circuit configured to adjust a phase of said transition sampling clock according to said adjustment signal.
7. An apparatus comprising:
a first sampling circuit configured to generate detected data in response to a data sampling clock;
a second sampling circuit configured to generate transition data in response to a transition sampling clock;
a phase detector circuit configured to generate a first phase adjustment signal and a second phase adjustment signal in response to said detected data, said transition data, a first control parameter and a second control parameter, wherein (A) a point at which a phase of said transition sampling clock settles after convergence is biased from a median value of a receiver eye jitter distribution based on a target bit error rate of an inner eye, (B) said first control parameter sets a threshold limit for increasing said phase of said transition sampling clock, and (C) said second control parameter sets a threshold limit for decreasing said phase of said transition sampling clock.
8. The apparatus according to claim 7 , wherein an amount of bias is selected based on said target bit error rate (BER).
9. The apparatus according to claim 7 , wherein said first and said second control parameters are programmable.
10. The apparatus according to claim 7 , wherein said phase detector circuit comprises:
an oversampled phase detector configured to generate a first control signal for increasing said phase of said transition sampling clock and a second control signal for decreasing said phase of said transition sampling clock;
a first accumulator configured to generate a first filtered control signal in response to said first control signal;
a second accumulator configured to generate a second filtered control signal in response to said second control signal;
a first comparator configured to generate said first phase adjustment signal in response to said first filtered control signal and said first control parameter;
a second comparator configured to generate said second phase adjustment signal in response to said second filtered control signal and said second control parameter.
11. An apparatus comprising:
a plurality of phase detector circuits each configured to generate a phase up signal and a phase down signal in response to a respective pair of data samples and intervening transition samples; and
a summing circuit configured to generate an adjustment signal in response to said phase up and phase down signals of said plurality of phase detector circuits, wherein a sum of said phase up signals and a sum of said phase down signals are weighted to provide a bias to a phase adjustment, wherein (i) said phase up signals are weighted by said first control parameter, (ii) said phase down signals are weighted by said second control parameter, and (iii) a ratio of said first control parameter and said second control parameter is set based on said target bit error rate of said inner eye.