IP Library Granted Patent US 9,595,594
Granted Patent B2
US 9,595,594 · App. 13/868,429 · Granted Mar 14, 2017

Compound semiconductor device and method for manufacturing the same

Inventor: Lei Zhu (Atsugi, JP)
Assignee: FUJITSU LIMITED
H01L29/66431H01L29/1075H01L29/1079H01L29/2003H01L29/4232H01L29/66462H01L29/778H01L29/7787H01L29/7789H02M3/335H02M3/33507H03F1/3241H03F3/195H03F3/1935H03F3/24
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Quick Facts
Patent No.
US 9,595,594
App. No.
13/868,429
Granted
Mar 14, 2017
Kind
B2
Abstract

A compound semiconductor device includes: a compound semiconductor region having a surface in which a step is formed; a first electrode formed so as to overlie the upper surface of the step, the upper surface being a non-polar face; and a second electrode formed along a side surface of the step so as to be spaced apart from the first electrode in a vertical direction, the side surface being a polar face.

Claims (34)

1. A compound semiconductor device, comprising:

a compound semiconductor region having a surface in which a step is formed;

a first electrode formed on an upper surface of the step, the upper surface being a non-polar face;

a second electrode formed along one side surface of the step so as to be spaced apart from the first electrode in a vertical direction, the one side surface being a polar face, and

a third electrode formed along another side surface of the step so as to be spaced apart from the first electrode in a horizontal direction, the another side surface being a polar face,

wherein a vertical distance between a lower surface of the first electrode and an upper surface of the second electrode is longer than a vertical distance between the lower surface of the first electrode and a lower surface of the third electrode,

wherein a first n-doped region is formed so as to underlie the third electrode in the step, and

wherein a second n-doped region is formed in the step between the first electrode and the third electrode, and a dopant concentration is lower in the second n-doped region than in the first n-doped region.

2. The compound semiconductor device according to claim 1 ,

wherein the step is in the form of a protrusion.

3. A method for manufacturing a compound semiconductor device, the method comprising:

forming a step in a surface of a compound semiconductor region;

forming a first electrode on an upper surface of the step, the upper surface being a non-polar face;

forming a second electrode along one side surface of the step, the second electrode being spaced apart from the first electrode in a vertical direction, the one side surface being a polar face, and

forming a third electrode along another side surface of the step, the third electrode being spaced apart from the first electrode in a horizontal direction, the another side surface being a polar face,

wherein a vertical distance between a lower surface of the first electrode and an upper surface of the second electrode is longer than a vertical distance between the lower surface of the first electrode and a lower surface of the third electrode,

wherein a first n-doped region is formed in the step so as to underlie the third electrode, and

wherein a second n-doped region is formed in the step between the first electrode and the third electrode, and a dopant concentration is lower in the second n-doped region than in the first n-doped region.

4. The method for manufacturing a compound semiconductor device according to claim 3 ,

wherein the step is in the form of a protrusion.

5. A compound semiconductor device, comprising:

a compound semiconductor region having a surface in which a step is formed;

a first electrode formed on an upper surface of the step, the upper surface being a non-polar face;

a second electrode formed along one side surface of the step so as to be spaced apart from the first electrode in a vertical direction, the one side surface being a polar face, and

a third electrode formed along another side surface of the step so as to be spaced apart from the first electrode in a horizontal direction, the another side surface being a polar face,

wherein a first n-doped region is formed so as to underlie the third electrode in the step, and

wherein a second n-doped region is formed in the step between the first electrode and the third electrode, and a dopant concentration is lower in the second n-doped region than in the first n-doped region.

6. A method for manufacturing a compound semiconductor device, the method comprising:

forming a step in a surface of a compound semiconductor region;

forming a first electrode on an upper surface of the step, the upper surface being a non-polar face;

forming a second electrode along one side surface of the step, the second electrode being spaced apart from the first electrode in a vertical direction, the one side surface being a polar face, and

forming a third electrode along another side surface of the step, the third electrode being spaced apart from the first electrode in a horizontal direction, the another side surface being a polar face,

wherein a first n-doped region is formed in the step so as to underlie the third electrode, and

wherein a second n-doped region is formed in the step between the first electrode and the third electrode, and a dopant concentration is lower in the second n-doped region than in the first n-doped region.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 3, 2013
From: ZHU, LEI
To: FUJITSU LIMITED
Reel/Frame 030345/0840 →
Priority Claims (1)
JP 2012-137281 · Jun 18, 2012 · national
Continuity (1)
Related Publication 20130337619A1 · Dec 19, 2013