IP Library Granted Patent US 9,065,627
Granted Patent B2
US 9,065,627 · App. 13/873,623 · Granted Jun 23, 2015

Differential timing transfer over synchronous ethernet using digital frequency generators and control word signaling

Inventors: James Aweya (Kanata, CA); Michel Ouellette (Orleans, CA); Delfin Y. Montuno (Kanata, CA)
Assignee: RPX Clearinghouse LLC
H04L7/0079G06F1/0328H03L7/0805H03L7/085H03L7/089H03L2207/50H04J3/0632H04J3/0658
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Quick Facts
Patent No.
US 9,065,627
App. No.
13/873,623
Granted
Jun 23, 2015
Kind
B2
Abstract

Transfer of differential timing over a packet network is provided. A transmitting service interface receives a service clock and is coupled to a receiving service interface through a network backplane. A primary reference clock is provided to time the network backplane. The primary reference clock and the service clock are used to synthesize a copy of the service clock connected to the transmitting service interface. A first control word containing an error differential between the service clock and the synthesized copy of the service clock is generated and transmitted through the network backplane via a packet. The first control word, together with the primary reference clock, is used to recreate the service clock for timing the receiving service interface.

Claims (29)

1. A system for transferring differential timing over a packet network, the packet network having a network backplane timed by a scaled primary reference clock, the system comprising a receiving service interface communicatively coupled to the network backplane and configured to:

receive, from a transmitting service interface, a first control word, the first control word indicating an error differential between a service clock connected to the transmitting service interface and a copy of the service clock synthesized by a master digital oscillator at the transmitting service interface using the scaled primary reference clock; and

use the first control word and the scaled primary reference clock at a slave digital oscillator to recreate the service clock for timing the receiving service interface.

2. The system of claim 1 , wherein a nominal control word is known by the receiving service interface and the first control word comprises at least one correlation sample.

3. The system of claim 1 , wherein the receiving service interface is configured to map the first control word into a second control word usable by the slave digital oscillator, the mapping being based on a difference between the master digital oscillator and the slave digital oscillator.

4. The system of claim 1 , wherein the receiving service interface is configured to receive updated control words and apply the updated control words to the service clock defining the receiving service interface.

5. A method of operating a receiving service interface of a system for transferring differential timing over a packet network, the packet network having a network backplane timed by a scaled primary reference clock, the method comprising:

receiving, from a transmitting service interface, a first control word, the first control word indicating an error differential between a service clock connected to the transmitting service interface and a copy of the service clock synthesized by a master digital oscillator at the transmitting service interface using the scaled primary reference clock; and

using the first control word and the scaled primary reference clock at a slave digital oscillator to recreate the service clock for timing the receiving service interface.

6. The method of claim 5 , wherein a nominal control word is known by the receiving service interface and the first control word comprises at least one correlation sample.

7. The method of claim 5 , further comprising mapping the first control word into a second control word usable by the slave digital oscillator, the mapping being based on a difference between the master digital oscillator and the slave digital oscillator.

8. The method of claim 5 , further comprising receiving updated control words and applying the updated control words to the service clock defining the receiving service interface.

9. A method of operating a transmitting service interface of a system for transferring differential timing over a packet network, the packet network having a network backplane timed by a scaled primary reference clock, the method comprising:

receiving a service clock;

generating a first control word containing an error differential between the service clock and a synthesized copy of the service clock synthesized using the scaled primary reference clock;

inputting the first control word to a digital oscillator, the digital oscillator providing the synthesized copy of the service clock based on the first control word; and

transmitting a packet containing the first control word on the network backplane toward the receiving service interface.

10. The method of claim 9 , further comprising controlling a time period of the digital oscillator using at least one clock state sampling.

11. The method of claim 9 , wherein the transmitting service interface comprises a digital phase-locked loop which is synthesized from a specification for an analog phase-locked loop based on the digitization of a continuous-time system to a corresponding discrete-time system using a modified pole-zero method.

12. The method of claim 11 , wherein the modified pole-zero method comprises:

mapping s-plane poles and zeros of the analog phase-locked loop into z-plane poles and zeros;

forming a discrete-time transfer function using the z-plane poles and zeros; and

setting a low-frequency gain of the discrete-time system substantially equal to that of the continuous-time system.

13. The method of claim 9 , further comprising:

updating the first control word at a periodic interval; and

transmitting a packet containing the updated control word on the network backplane toward the receiving service interface.

14. The method of claim 9 , wherein the transmitting service interface comprises a digital phase-locked loop comprising a phase-frequency detector, a loop filter and a master digital oscillator.

15. The method of claim 14 , wherein the master digital oscillator is one of a direct digital synthesizer and a divide-by-N counter oscillator.

16. The method of claim 15 , wherein the first control word is used to control the master digital oscillator.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Oct 26, 2020
From: JEFFERIES FINANCE LLC
To: RPX CLEARINGHOUSE LLC
Reel/Frame 054305/0505 →
SECURITY INTEREST Recorded Jun 29, 2018
From: RPX CLEARINGHOUSE LLC
To: JEFFERIES FINANCE LLC
Reel/Frame 046485/0644 →
RELEASE (REEL 038041 / FRAME 0001) Recorded Jan 2, 2018
From: JPMORGAN CHASE BANK, N.A.
To: RPX CORPORATION; RPX CLEARINGHOUSE LLC
Reel/Frame 044970/0030 →
SECURITY AGREEMENT Recorded Mar 9, 2016
From: RPX CORPORATION; RPX CLEARINGHOUSE LLC
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038041/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 9, 2015
From: ROCKSTAR CONSORTIUM US LP; ROCKSTAR CONSORTIUM LLC; BOCKSTAR TECHNOLOGIES LLC; CONSTELLATION TECHNOLOGIES LLC; MOBILESTAR TECHNOLOGIES LLC; NETSTAR TECHNOLOGIES LLC
To: RPX CLEARINGHOUSE LLC
Reel/Frame 034924/0779 →
Continuity (2)
Continuation 12268008 · Nov 10, 2008
Related Publication 20130235889A1 · Sep 12, 2013