Charge distribution
A charge distributor comprises a charge generator configured to output a charge, a current conveyor, and a plurality of output stages. The current conveyor is configured to receive the charge from the charge generator as an input and to couple this charge to a plurality of output stages. A first output stage, of the plurality of output stages, comprises a plurality of current mirrors. The plurality of current mirrors is configured to mirror and scale the charge received from the current conveyor into a scaled mirrored charge. The first output stage is configured to provide the scaled mirrored charge as an output.
1. A charge distributor comprising:
a charge generator configured to output a charge;
a current conveyor configured to receive said charge as an input and to couple said charge to a plurality of output stages; and
a first output stage, of said plurality of output stages, said first output stage comprising a plurality of current mirrors configured to mirror and scale said charge received from said current conveyor into a scaled mirrored charge, wherein said first output stage is configured to provide said scaled mirrored charge as an output.
2. The charge distributor of claim 1 , wherein an amount of scaling accomplished by said plurality of current mirrors is fixed.
3. The charge distributor of claim 1 , wherein an amount of scaling accomplished by said plurality of current mirrors is variable.
4. The charge distributor of claim 1 , wherein said plurality of mirrors comprise a plurality of binary weighted mirrors which provide n-bit scalability when mirroring said charge received from said current conveyor.
5. The charge distributor of claim 4 , wherein said n-bit scalability is variable in response to an input received by said first output stage.
6. The charge distributor of claim 1 , wherein said plurality of current mirrors are implemented with metal oxide semiconductor field effect transistors.
7. The charge distributor of claim 1 , wherein said plurality of current mirrors are cascoded.
8. The charge distributor of claim 1 , wherein said first output stage is implemented with no capacitors.
9. The charge distributor of claim 1 , wherein said plurality of current mirrors provide a bidirectional scaled mirrored charge as an output.
10. The charge distributor of claim 1 , wherein said plurality of current mirrors provide a unidirectional scaled mirrored charge as an output.
11. An analog-to-digital convertor comprising:
a charge distributor comprising:
a first output stage, of a plurality of output stages, said first output stage comprising a plurality of current mirrors configured to mirror and scale a charge received from a current conveyor into a scaled mirrored charge, wherein said first output stage is configured to provide said scaled mirrored charge as an output; and
a delta sigma modulator configured to receive an analog sample and convert said analog sample into a digital output, said delta sigma modulator coupled with said charge distributor and configured utilize a plurality of scaled mirrored charge outputs from said charge distributor as feedback charges.
12. The analog-to-digital convertor of claim 11 , wherein said plurality of mirrors comprise a plurality of binary weighted mirrors which provide n-bit scalability when mirroring said charge received from said current conveyor.
13. The analog-to-digital convertor of claim 11 , wherein scalability of said scaled mirrored charged by said first output is fixed.
14. The analog-to-digital convertor of claim 11 , wherein scalability of said scaled mirrored charged by said first output is variable.
15. The analog-to-digital convertor of claim 11 , wherein said first output stage is implemented with no capacitors.
16. An input device comprising:
a processing system configured for determining a user input based upon a capacitive interaction of an input object with a sensor electrode; and
a charge distributor comprising:
a charge generator configured to output a charge;
a current conveyor configured to receive said charge as an input and to couple said charge to a plurality of output stages; and
a first output stage, of said plurality of output stages, said first output stage comprising a plurality of current mirrors configured to mirror and scale said charge received from said current conveyor into a scaled mirrored charge, wherein said first output stage is configured to provide said scaled mirrored charge as an output; and
wherein said scaled mirrored charge is coupled within said input device in a manner that subtracts charge from a sensor electrode charge received by said processing system as an input from said sensor electrode.
17. The input device of claim 16 , wherein said plurality of mirrors comprise a plurality of binary weighted mirrors which provide n-bit scalability when mirroring said charge received from said current conveyor.
18. The input device of claim 16 , wherein scalability of said scaled mirrored charged by said first output is fixed.
19. The input device of claim 16 , wherein scalability of said scaled mirrored charged by said first output is variable.
20. The input device of claim 16 , wherein said first output stage is implemented with no capacitors.