Systems and methods for sync mark mis-detection protection
View Patent ↗The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for detecting patterns in a data stream. As an example, a data processing system is discussed that includes a sync mark detection circuit and a sync quality output circuit. The sync mark detection circuit is operable to identify a predefined pattern in a received data set, where identification of the predefined pattern results is asserting a sync found output, and where a preamble pattern precedes the predefined pattern in the received data set. The sync quality output circuit is operable to provide a sync mark quality metric indicating a similarity between the preamble pattern and the received data set within a region preceding the predefined pattern.
1. A data processing system, the system comprising:
a sync mark detection circuit operable to identify a predefined pattern in a received data set, wherein identification of the predefined pattern results in asserting a sync found output at a first location;
a distance calculation circuit operable to determine a distance from a second location of a preceding occurrence to the first location assertion of the sync found output, wherein the second location is different from the first location; and
a sync output circuit operable to assert a sync mark detected output corresponding to the sync found output when the distance is less than a threshold value.
2. The data processing system of claim 1 , wherein the threshold value is programmable.
3. The data processing system of claim 1 , wherein the threshold value is greater than the length of the predefined pattern.
4. The data processing system of claim 1 , wherein the received data set further includes a preamble pattern, and wherein the preceding occurrence is a detected end of the preamble pattern.
5. The data processing system of claim 4 , wherein the preamble pattern is a defined length.
6. The data processing system of claim 5 , wherein the defined length is greater than the length of the predefined pattern.
7. The data processing system of claim 1 , wherein the sync output circuit is further operable to assert a mis-identified sync output when the sync found output is asserted when the distance is greater than the threshold value.
8. The data processing system of claim 1 , wherein the system is implemented as part of an integrated circuit.
9. The data processing system of claim 1 , wherein the system is implemented as part of a device selected from a group consisting of: a storage device and a wireless communication device.
10. The data processing system of claim 1 , wherein the received data is derived from a user data region of a storage medium.
11. The data processing system of claim 10 , wherein the preceding occurrence is within the user data region of the storage medium.
12. The data processing system of claim 10 , wherein the preceding occurrence is within a servo data region of the storage medium, and wherein the servo data region directly precedes the user data region.
13. A data processing system, the system comprising:
a sync mark detection circuit operable to identify a predefined pattern in a received data set, wherein identification of the predefined pattern results in asserting a sync found output, and wherein a preamble pattern precedes the predefined pattern in the received data set;
a sync quality output circuit operable to provide a sync mark quality metric indicating a similarity between the preamble pattern and the received data set within a region preceding the predefined pattern; and
a sync output circuit operable to assert a sync mark detected output corresponding to the sync found output when the sync mark quality metric is less than a threshold value.
14. The data processing system of claim 13 , wherein the threshold value is programmable.
15. The data processing system of claim 14 , wherein the threshold value is greater than the length of the predefined pattern.
16. The data processing system of claim 13 , wherein the sync output circuit is further operable to assert a mis-identified sync output when the sync found output is asserted when the distance is greater than the threshold value.
17. The data processing system of claim 13 , wherein the system is implemented as part of an integrated circuit.
18. The data processing system of claim 13 , wherein the system is implemented as part of a device selected from a group consisting of: a storage device and a wireless communication device.
19. The data processing system of claim 13 , wherein the received data is derived from a user data region of a storage medium.