Permutable switching network with enhanced interconnectivity for multicasting signals

1. An integrated circuit, comprising: a L-level permutable switching network (L-PSN),

wherein the L-PSN comprises (L+2) levels of conductors and (L+1) sets of switches:

wherein the (L+2) levels of conductors comprises:

for i=[1:L], (I[i]/D[i])>1, D[i]>1, L≧1, each of the i-th level of conductors comprises I[i] number of conductors comprising D[i] sets of conductors;

an 0-th level of conductors of I[0] number of conductors,

wherein (I[0]/Π i=[1:L] D[i])>1; and

an (L+1)-th level of conductors of I[L+1] number of conductors comprising D[L+1] sets of conductors,

wherein D[L+1]>2 and each of the D[L+1] sets of conductors comprises Π= i=[1:L] D[i] number of conductors;

wherein each i-th set of the (L+1) sets of switches comprises (I[i−1]×D[i]) number of switches for i=[1:L+1];

wherein the I[i−1] number of conductors of the (i−1)-th level of conductors selectively couple to (I[i]/D[i]) number of conductors in each of the D[i] sets of conductors of the i-th level of conductors through a respective I[i−1] number of switches of the i-th set of switches for i=[1:L+1] without requiring traversal of any other conductors;

a j-th level of I[j] number of conductors comprising D[j] sets of (I[j]/D[j]) number of conductors for at least one j selected from [1:L+1], a prime number k>1 and D S [j]=D[j]×(I[j−1]/I[j]);

the I[j−1] number of conductors of the (j−1)-th level of conductors are organized into (I[j−1]/D S [j]) groups of D S [j] number of conductors,

wherein, for m=[1: D S [j]], the D S [j] number of conductors of each (I[j−1]/D S [j]) groups of conductors, consisting of the q[m]-th conductor of the I[j−1] number of conductors of the (j−1)-th level of conductors, are selected from the I[j−1] number of conductors according to a prime k sequence,

wherein each of the adjacent q[m]-th conductor of the D S [j] number of conductors is separated by the prime number k, and

wherein each of the D S [j] number of conductors selectively couple to one conductor of the (I[j]/D[j]) number of conductors of one of the D[j] sets of conductors of the j-th level of conductors through a respective D S [j] number of switches of the j-th set of switches without requiring traversal of any other conductors;

wherein at least one group of the (I[j−1]/D S [j]) groups of D S [j] number of conductors selectively couple to at least (D[j]+1) number of conductors of the j-th level of conductors through (D S [j]×D[j]) number of switches of the j-th level of switches without requiring traversal of any other conductors, and

wherein the at least (D[j]+1) number of conductors comprises at least one conductor selected from each of the D[j] sets of conductors.

2. The integrated circuit of claim 1 , wherein the Π i=[1:L] D[i] number of conductors in each of the D[L+1] sets of conductors of the (L+1)-th level of conductors are physically connected to a corresponding number of pins of a corresponding module selected from switching networks and logic cells.

3. The integrated circuit of claim 1 , wherein any D S [j] number of conductors of the (j−1)-th level of I[j−1] number of conductors selectively couple to at least (D[j]+1) number of conductors of the I[j] number of conductors of the j-th level of conductors through the (D S [j]×D[j]) number of switches without requiring traversal of any other conductors, and wherein the at least (D[j]+1) number of conductors comprises at least one conductor selected from each of the D[j] sets of conductors of the j-th level of conductors.

4. The integrated circuit of claim 1 , wherein for any SC>0 and (I[j]−D[j]+1)≧SC, the SC number of conductors of the I[j−1] number of conductors selectively couple to CC number of conductors of the D[j] sets of conductors through (SC×D[j]) number of switches of the j-th set of switches without requiring traversal of any other conductors,

wherein the CC number of conductors comprises at least one conductor selected from each of the D[j] sets of conductors, and wherein CC is at least (SC+D[j]−1).

5. The integrated circuit of claim 1 , wherein for I[j]≧(D[j]×(D[j]×D S [j])), any D S [j] number of conductors of the I[j−1] number of conductors selectively couple to CC number of conductors of the D[j] sets of conductors through (D S [j]×D[j]) number of switches of the j-th set of switches without requiring traversal of any other conductors,

wherein the CC number of conductors comprises at least one conductor selected from each of the D[j] sets of conductors, and wherein CC is at least (D S [j]×(D[j]−1)+1).

6. A method of manufacturing an integrated circuit, comprising:

fabricating a L-level permutable switching network (L-PSN),

wherein the L-PSN comprises (L+2) levels of conductors and (L+1) sets of switches:

wherein the (L+2) levels of conductors comprises:

for i=[1:L], (I[i]/D[i])>1, D[i]>1, L≧1, each of the i-th level of conductors comprises I[i] number of conductors comprising D[i] sets of conductors;

an 0-th level of conductors of I[0] number of conductors,

wherein (I[0]/Π i=[1:L] D[i])>1; and

an (L+1)-th level of conductors of I[L+1] number of conductors comprising D[L+1] sets of conductors,

wherein D[L+1]>2 and each of the D[L+1] sets of conductors comprises Π i=[1:L] D[i] number of conductors;

wherein each i-th set of the (L+1) sets of switches comprises (I[i−1]×D[i]) number of switches for i=[1:L+1];

selectively coupling the I[i−1] number of conductors of the (i−1)-th level of conductors to (I[i]/D[i]) number of conductors in each of the D[i] sets of conductors of the i-th level of conductors through a respective I[i−1] number of switches of the i-th set of switches for i=[1:L+1] without requiring traversal of any other conductors;

a j-th level of I[j] number of conductors comprising D[j] sets of (I[j]/D[j]) number of conductors for at least one j selected from [1:L+1], a prime number k>1 and D S [j]=D[j]×(I[j−1]/I[j]);

the I[j−1] number of conductors of the (j−1)-th level of conductors are organized into (I[j−1]/D S [j]) groups of D S [j] number of conductors,

wherein, for m=[1:D S [j]], the D S [j] number of conductors of each (I[j−1]/D S [j]) groups of conductors, consisting of the q[m]-th conductor of the I[j−1] number of conductors of the (j−1)-th level of conductors, are selected from the I[j−1] number of conductors according to a prime k sequence,

wherein each of the adjacent q[m]-th conductor of the D S [j] number of conductors is separated by the prime number k, and

selectively coupling each of the D S [j] number of conductors to one conductor of the (I[j]/D[j]) number of conductors of one of the D[j] sets of conductors of the j-th level of conductors through a respective D S [j] number of switches of the j-th set of switches without requiring traversal of any other conductors;

selectively coupling at least one group of the (I[j−1]/D S [j]) groups of D S [j] number of conductors to at least (D[j]+1) number of conductors of the j-th level of conductors through (D S [j]×D[j]) number of switches of the j-th level of switches without requiring traversal of any other conductors, and

wherein the at least (D[j]+1) number of conductors comprises at least one conductor selected from each of the D[j] sets of conductors.

7. The method of claim 6 , further comprising physically coupling the Π i=[1:L] D[i] number of conductors in each of the D[L+1] sets of conductors of the (L+1)-th level of conductors to a corresponding number of pins of a corresponding module selected from switching networks and logic cells.

8. The method of claim 6 , further comprising selectively coupling any D S [j] number of conductors of the (j−1)-th level of I[j−1] number of conductors to at least (D[j]+1) number of conductors of the I[j] number of conductors of the j-th level of conductors through the (D S [j]×D[j]) number of switches without requiring traversal of any other conductors, and wherein the at least (D[j]+1) number of conductors comprises at least one conductor selected from each of the D[j] sets of conductors of the j-th level of conductors.

9. The method of claim 6 , further comprising, for any SC>0 and (I[j]−D[j]+1)≧SC, selectively coupling the SC number of conductors of the I[j−1] number of conductors to CC number of conductors of the D[j] sets of conductors through (SC×D[j]) number of switches of the j-th set of switches without requiring traversal of any other conductors, wherein the CC number of conductors comprises at least one conductor selected from each of the D[j] sets of conductors, and wherein CC is at least (SC+D[j]−1).

10. The method of claim 6 , further comprising, for I[j]>(D[j]×(D[j]×D S [j])), selectively coupling any D S [j] number of conductors of the I[j−1] number of conductors to CC number of conductors of the D[j] sets of conductors through (D S [j]×D[j]) number of switches of the j-th set of switches without requiring traversal of any other conductors, wherein the CC number of conductors comprises at least one conductor selected from each of the D[j] sets of conductors, and wherein CC is at least (D S [j]×(D[j]−1)+1).

11. A non-transitory machine readable storage medium that stores data representing an integrated circuit layout which when executed by a computing machine cause the computing machine to provide the integrated circuit layout comprising a L-level permutable switching network (L-PSN), wherein the L-PSN comprises (L+2) levels of conductors and (L+1) sets of switches:

wherein the (L+2) levels of conductors comprises:

for i=[1:L], (I[i]/D[i])>1, D[i]>1, L≧1, each of the i-th level of conductors comprises I[i] number of conductors comprising D[i] sets of conductors;

an 0-th level of conductors of I[0] number of conductors,

wherein (I[0]/Π i=[1:L] D[i]>1; and

an (L+1)-th level of conductors of I[L+1] number of conductors comprising D[L+1] sets of conductors,

wherein D[L+1]>2 and each of the D[L+1] sets of conductors comprises Π i=[1:L] D[i] number of conductors;

wherein each i-th set of the (L+1) sets of switches comprises (I[i−1]×D[i]) number of switches for i=[1:L+1];

wherein the I[i−1] number of conductors of the (i−1)-th level of conductors selectively couple to (I[i]/D[i]) number of conductors in each of the D[i] sets of conductors of the i-th level of conductors through a respective I[i−1] number of switches of the i-th set of switches for i=[1:L+1] without requiring traversal of any other conductors;

a j-th level of I[j] number of conductors comprising D[j] sets of (I[j]/D[j]) number of conductors for at least one j selected from [1:L+1], a prime number k>1 and D S [j]=D[j]×(I[j−1]/I[j]);

the I[j−1] number of conductors of the (j−1)-th level of conductors are organized into (I[j−1]/D S [j]) groups of D S [j] number of conductors,

wherein, for m=[1: D S [j]], the D S [j] number of conductors of each (I[j−1]/D S [j]) groups of conductors, consisting of the q[m]-th conductor of the I[j−1] number of conductors of the (j−1)-th level of conductors, are selected from the I[j−1] number of conductors according to a prime k sequence,

wherein each of the adjacent q[m]-th conductor of the D S [j] number of conductors is separated by the prime number k, and

wherein each of the D S [j] number of conductors selectively couple to one conductor of the (I[j]/D[j]) number of conductors of one of the D[j] sets of conductors of the j-th level of conductors through a respective D S [j] number of switches of the j-th set of switches without requiring traversal of any other conductors;

wherein at least one group of the (I[j−1]/D S [j]) groups of D S [j] number of conductors selectively couple to at least (D[j]+1) number of conductors of the j-th level of conductors through (D S [j]×D[j]) number of switches of the j-th level of switches without requiring traversal of any other conductors, and

wherein the at least (D[j]+1) number of conductors comprises at least one conductor selected from each of the D[j] sets of conductors.

12. The non-transitory machine readable storage medium of claim 11 , wherein the Π i=[1:L] D[i] number of conductors in each of the D[L+1] sets of conductors of the (L+1)-th level of conductors are physically connected to a corresponding number of pins of a corresponding module selected from switching networks and logic cells.

13. The non-transitory machine readable storage medium of claim 11 , wherein any D S [j] number of conductors of the (j−1)-th level of I[j−1] number of conductors selectively couple to at least (D[j]+1) number of conductors of the I[j] number of conductors of the j-th level of conductors through the (D S [j]×D[j]) number of switches without requiring traversal of any other conductors, and wherein the at least (D[j]+1) number of conductors comprises at least one conductor selected from each of the D[j] sets of conductors of the j-th level of conductors.

14. The non-transitory machine readable storage medium of claim 11 , wherein for any SC>0 and (I[j]−D[j]+1)≧SC, the SC number of conductors of the I[j−1] number of conductors selectively couple to CC number of conductors of the D[j] sets of conductors through (SC×D[j]) number of switches of the j-th set of switches without requiring traversal of any other conductors,

wherein the CC number of conductors comprises at least one conductor selected from each of the D[j] sets of conductors, and wherein CC is at least (SC+D[j]−1).

15. The non-transitory machine readable storage medium of claim 11 , wherein for I[j]≧(D[j]×(D[j]×D S [j])), any D S [j] number of conductors of the I[j−1] number of conductors selectively couple to CC number of conductors of the D[j] sets of conductors through (D S [j]×D[j]) number of switches of the j-th set of switches without requiring traversal of any other conductors,

wherein the CC number of conductors comprises at least one conductor selected from each of the D[j] sets of conductors, and wherein CC is at least (D S [j]×(D[j]−1)+1).