SRAM with via displacement
The SRAM memory cell includes a metal wiring line having a titanium or tantalum film in a bottom layer, and a via having a tungsten plug. The via is arranged on the metal line following a layout rule which permits the misalignment. In arranging the upper-layer via with a tungsten plug on the metal line, one side of the via is disposed to be adjacent to one end of the metal line with a margin smaller than an alignment accuracy, and the lower-layer via is laid out far away from the end of the metal line as possible. The reduction in the yield, caused by the problem of the contact with the lower-layer via being broken or increased in resistance at occurrence of misalignment, can be suppressed.
1. An SRAM comprising a plurality of memory cells arranged in a matrix form, each memory cell including:
(a) a substrate with MOSFET formed therein;
(b) a contact for forming an electrical connection with the MOSFETs;
(c) a first wiring line which is electrically connected with the contact, and formed by a first wiring layer having a metal layer of titanium or tantalum in a plane in touch with the contact, and which has a width as large as a minimum line width in the first wiring layer;
(d) a first via which has a tungsten plug and is electrically connected with the first wiring line;
(e) a second wiring line which is electrically connected with the first via, and formed by a second wiring layer having a metal layer of titanium or tantalum in a plane in touch with the first via, and which has a width as large as a minimum line width in the second wiring layer; and
(f) a second via which is electrically connected with the second wiring line, and which has a tungsten plug and has one side as large as the minimum line width in the second wiring layer,
wherein the second wiring line extends in the same direction as that of the first wiring line extending in a row or column direction, and has a length of two to three times the minimum line width in the second wiring layer, and
in a plane in parallel with the substrate, the first via is disposed in a position between the contact and the second via, said contact, first via, and second via being displaced with respect to each other in a length direction of the second wiring line so that the distance between the first via and the contact is shorter than the distance between the contact and the second via, and the distance between the first and second vias is shorter than the distance between the contact and the second via.
2. The SRAM according to claim 1 , wherein the first via is disposed, in a plane in parallel with the substrate, in a position where the distance between the first and second vias is equal to the distance between the first via and the contact.
3. The SRAM according to claim 1 , wherein a direction in which the first wiring line extends is defined as a row direction,
each memory cell further includes:
(g) a third wiring line which is electrically connected with the second via, and formed by a third wiring layer, and which extends in a column direction orthogonal to the row direction at a cell boundary of the memory cell,
wherein the third wiring line is a ground line in the memory cell,
one memory cell which is mirror-inverted about the cell boundary in the row direction in a plane in parallel with the substrate coincides in layout with another memory cell adjacent to the one memory cell,
the second via which is mirror-inverted about the cell boundary in the row direction coincides with the second via of the adjacent memory cell, and
in one of the memory cells adjacent to each other, the layout of the first via is left out.
4. The SRAM according to claim 2 , wherein a direction in which the first wiring line extends is defined as a row direction,
each memory cell further includes:
(g) a third wiring line which is electrically connected with the second via, and formed by a third wiring layer, and which extends in a column direction orthogonal to the row direction at a cell boundary of the memory cell,
wherein the third wiring line is a ground line in the memory cell,
one memory cell which is mirror-inverted about the cell boundary in the row direction in a plane in parallel with the substrate coincides in layout with another memory cell adjacent to the one memory cell,
the second via which is mirror-inverted about the cell boundary in the row direction coincides with the second via of the adjacent memory cell, and
in one of the memory cells adjacent to each other, the layout of the first via is left out.
5. The SRAM according to claim 1 , wherein a direction in which the first wiring line extends is defined as a row direction,
each memory cell further includes:
(g) a third wiring line which is electrically connected with the second via, and formed by a third wiring layer, and which extends in a column direction orthogonal to the row direction at a cell boundary of the memory cell,
wherein the third wiring line is a ground line in the memory cell,
one memory cell which is mirror-inverted about the cell boundary in the row direction coincides in layout with another memory cell adjacent to the one memory cell,
the second via which is mirror-inverted about the cell boundary in the row direction coincides with the second via of the adjacent memory cell, and
the first vias are joined to each other in the adjacent memory cells adjacent to each other.
6. The SRAM according to claim 2 , wherein a direction in which the first wiring line extends is defined as a row direction,
each memory cell further includes:
(g) a third wiring line which is electrically connected with the second via, and formed by a third wiring layer, and which extends in a column direction orthogonal to the row direction at a cell boundary of the memory cell,
wherein the third wiring line is a ground line in the memory cell,
one memory cell which is mirror-inverted about the cell boundary in the row direction coincides in layout with another memory cell adjacent to the one memory cell,
the second via which is mirror-inverted about the cell boundary in the row direction coincides with the second via of the adjacent memory cell, and
the first vias are joined to each other in the adjacent memory cells adjacent to each other.
7. The SRAM according to claim 1 , wherein a direction in which the first wiring line extends is defined as a row direction,
each memory cell further includes:
(g) a third wiring line which is electrically connected with the second via, and formed by a third wiring layer, and which extends in a column direction orthogonal to the row direction,
wherein the third wiring line is a bit line in the memory cell.
8. The SRAM according to claim 2 , wherein, a direction in which the first wiring line extends is defined as a row direction,
each memory cell further includes:
(g) a third wiring line which is electrically connected with the second via, and formed by a third wiring layer, and which extends in a column direction orthogonal to the row direction,
wherein the third wiring line is a bit line in the memory cell.
9. An SRAM comprising a plurality of memory cells arranged in a matrix form, each memory cell including:
(a) a substrate with MOSFET formed therein;
(b) a contact for forming an electrical connection with the MOSFETs;
(c) a first wiring line which is electrically connected with the contact, and formed by a first wiring layer having a metal layer of titanium or tantalum in a plane in touch with the contact, and which has a width as large as a minimum line width in the first wiring layer, and a length of larger than the minimum line width and up to double the minimum line width; and
(d) a first via which has a tungsten plug and is electrically connected with the first wiring line,
wherein in a plane in parallel with the substrate, the first via is disposed to be adjacent to one end of a larger side of the first wiring line with a margin smaller than an alignment accuracy between the first via and the first wiring line, and
the contact is disposed on the other end of the longer side of the first wiring line.
10. The SRAM according to claim 9 , wherein each memory cell further includes:
(e) a second wiring line which is electrically connected with the first via, and formed by a second wiring layer, and which extends in a column direction orthogonal to a row direction,
wherein the second wiring line is a bit line in the memory cell.
11. An SRAM comprising a plurality of memory cells arranged in a matrix form,
each memory cell including:
(a) a substrate with MOSFET formed therein;
(d) a first via having a tungsten plug;
(e) a second wiring line which is electrically connected with the first via, and formed by a second wiring layer having a metal layer of titanium or tantalum in a plane in touch with the first via, and which has a width as large as a minimum line width in the second wiring layer, and a length of larger than the minimum line width and up to double the minimum line width;
(f) a second via which is electrically connected with the second wiring line, and which has a tungsten plug and has one side as large as the minimum line width in the second wiring layer,
wherein in a plane in parallel with the substrate, the second via is disposed to be adjacent to one end of a longer side of the second wiring line with a margin smaller than an alignment accuracy between the second via and the second wiring line, and
the first via is disposed on the other end of the longer side of the second wiring line.
12. The SRAM according to claim 11 , wherein each memory cell further includes:
(g) a third wiring line which is electrically connected with the second via, and formed by a third wiring layer,
wherein the third wiring line is a bit line in the memory cell.
13. An SRAM comprising a plurality of memory cells arranged in a matrix form, each memory cell including:
(a) a substrate with MOSFET formed therein;
(b) a contact for forming an electrical connection with the MOSFETs;
(c) a first wiring line which is electrically connected with the contact, and formed by a first wiring layer having a metal layer of titanium or tantalum in a plane in touch with the contact, and which has a width as large as a minimum line width in the first wiring layer;
(d) a first via which has a tungsten plug and is electrically connected with the first wiring line;
(e) a second wiring line which is electrically connected with the first via, and formed by a second wiring layer having a metal layer of titanium or tantalum in a plane in touch with the first via, and which has a width as large as a minimum line width in the second wiring layer; and
(f) a second via which is electrically connected with the second wiring line, and which has a tungsten plug and has one side as large as the minimum line width in the second wiring layer,
wherein the second wiring line extends in the same direction as that of the first wiring line extending in a row or column direction, is connected with a corresponding second wiring line in an adjacent memory cell, has a length of 4 to 8 times the minimum line width in the second wiring layer, and
in a plane in parallel with the substrate, the first via is disposed in a position between the contact and an adjacent second via in the adjacent memory cell, which corresponds to the second via, said contact, first via, and second via being displaced with respect to each other in a length direction of the second wiring line so that the distance between the first via and the contact is shorter than the distance between the contact and the adjacent second via, and the distance between the first via and the adjacent second, via is shorter than the distance between the contact and the adjacent second via.
14. The SRAM according to claim 13 , wherein the first via is disposed in a position where the distance between the adjacent second via and the first via is equal to the distance between the first via and the contact in a plane in parallel with the substrate.