Metal-oxide-semiconductor high electron mobility transistors and methods of fabrication
View Patent ↗A method of fabricating Group III-V semiconductor metal oxide semiconductor (MOS) and III-V MOS devices are described.
1. A method of fabricating a semiconductor device, the method comprising:
forming a first gate mask;
etching a recess in at least one semiconductor layer;
atomic layer depositing an oxide layer;
forming a second gate mask over the oxide layer;
forming a barrier layer over the oxide layer, wherein the forming of the barrier layer is before the forming of the second gate mask;
plating a seed layer over the barrier layer and
plating a gate over the oxide layer.
2. A method as claimed in claim 1 , further comprising providing a Group III-V semiconductor substrate and forming a plurality of epitaxial layers over the substrate prior to the forming the first gate mask.
3. A method as claimed in claim 2 , wherein the device is a high electron mobility transistor (HEMT) and at least one of the epitaxial layers is a buried channel layer.
4. A method as claimed in claim 1 , wherein all steps of the method are carried out at temperatures less than approximately 300° C.
5. A method as claimed in claim 1 , wherein the atomic layer deposition is a low temperature (LT) deposition method.
6. A method as claimed in claim 5 , wherein the LT deposition is carried out at a temperatures in the range of approximately 25° C. to approximately 150° C.
7. A method as claimed in claim 1 , further comprising, after the plating the gate, removing the second gate mask.
8. A method as claimed in claim 7 , wherein the barrier layer and the seed layer are disposed over the first mask layer and the recess, and the method further comprises: after removing the second gate mask, removing the seed layer and the barrier layer disposed over the first gate mask.
9. A method as claimed in claim 8 , further comprising, after removing the seed layer and the barrier layer disposed over the first mask, removing the first mask.
10. A method as claimed in claim 1 , wherein the method does not include a lift-off sequence to form the gate.
11. A method of fabricating a semiconductor device, the method comprising:
forming a first gate mask;
etching a recess in at least one semiconductor layer;
atomic layer depositing an oxide layer;
forming a second gate mask over the oxide layer;
forming a barrier layer comprising a refractory metal and a refractory metal alloy over the oxide layer; and
plating a gate over the oxide layer.
12. A method as claimed in claim 11 , wherein the forming of the barrier layer is before the forming of the second gate mask.
13. A method as claimed in claim 11 , further comprising forming a seed layer over the barrier layer.
14. A method as claimed in claim 13 , wherein the forming the seed layer further comprises plating the seed layer over the barrier layer.
15. A method as claimed in claim 14 , further comprising, after the plating the gate, removing the second gate mask.
16. A method as claimed in claim 11 , further comprising providing a Group III-V semiconductor substrate and forming a plurality of epitaxial layers over the substrate prior to the forming the first gate mask.
17. A method as claimed in claim 16 , wherein the device is a high electron mobility transistor (HEMT) and at least one of the epitaxial layers is a buried channel layer.
18. A method as claimed in claim 11 , wherein all steps of the method are carried out at temperatures less than approximately 300° C.
19. A method as claimed in claim 11 , wherein the atomic layer deposition is a low temperature (LT) deposition method.
20. A method as claimed in claim 19 , wherein the LT deposition is carried out at a temperatures in the range of approximately 25° C. to approximately 150° C.