Double output linearized low-noise charge pump with loop filter area reduction
According to embodiments, dual path loop filter circuits are described which have, for example, a single charge pump. The current flow in the DPLF circuit is architected to source, during an injection time period, a first current to the loop filter, sink, also during the injection time period, a second current from the loop filter, wherein the first current has a magnitude of α*I and the second current has a magnitude of β*I, and sink, during a linearization time period, a third current from the loop filter, wherein the third current has a magnitude of (α−β)*I.
1. A loop filter circuit comprising:
a loop filter including a first capacitor and a second capacitor; and
a current source circuit configured to:
(a) source, during an injection time period, a first current to the first capacitor of the loop filter;
(b) sink, during the injection time period, a second current from the
second capacitor of the loop filter, wherein the first current has a magnitude of α*I and the second current has a magnitude of β*I; and
(c) sink, during a linearization time period, a third current from the loop filter, wherein the third current has a magnitude of (α−β)*I,
wherein I is a current having a predetermined magnitude, and α and β are constants.
2. The loop filter circuit of claim 1 , wherein the loop filter circuit is a dual path loop filter (DPLF) having only a single charge pump.
3. The loop filter circuit of claim 2 , wherein the single charge pump is linearized during the linearization time period.
4. The loop filter circuit of claim 1 , further comprising:
a memorization circuit configured to copy the first current during a recopy time period in order to reduce noise.
5. The loop filter circuit of claim 1 , wherein the current source circuit includes a single current source configured to generate a reference current I and a current mirror circuit configured to generate the first, second and third currents using the reference current I.
6. The loop filter circuit of claim 1 , wherein a length of the linearization time period is constant.
7. The loop filter circuit of claim 1 , wherein the current source circuit is further configured to sink, during a tracking phase, a fourth current from the first capacitor.
8. A method for sinking and sourcing current to a loop filter comprising:
sourcing, during an injection time period, a first current to the loop filter;
sinking, during the injection time period, a second current from the loop filter;
wherein the first current has a magnitude of α*I and the second current has a magnitude of β*I; and
sinking, during a linearization time period, a third current from the loop filter,
wherein the third current has a magnitude of (α−β)*I,
wherein I is a current having a predetermined magnitude, and α and β are constants.
9. The method of claim 8 , wherein the loop filter circuit is a dual path loop filter (DPLF) having only a single charge pump.
10. The method of claim 8 , wherein the single charge pump is linearized due to the linearization time period.
11. The method of claim 8 , further comprising:
copying the first current during a recopy time period in order to reduce noise.
12. The method of claim 8 , further comprising:
generating a reference current I using a single current source; and
generating the first, second and third currents using the reference current I and a current mirror.
13. The method of claim 8 , wherein a length of the linearization time period is constant.
14. The method of claim 8 , wherein a length of the linearization time period is proportional to a VCO period.
15. The method of claim 8 , further comprising:
sinking, during a tracking time period, a fourth current from the loop filter.
16. A phase locked loop (PLL) circuit comprising:
a loop filter including a first capacitor and a second capacitor;
a current source configured to generate a reference current I;
a memorization current source circuit configured to generate a source current having a magnitude of α*I, and to provide the source current to the first capacitor of the loop filter during an injection time period;
a current mirror circuit configured to receive a first sunk current from the second capacitor during the injection time period having a magnitude of β*I and to receive a second sunk current from the loop filter during a linearization time period having a magnitude of (α−β)*I.
17. The PLL circuit of claim 16 , wherein the loop filter circuit is a dual path loop filter (DPLF) having only a single charge pump.
18. The PLL circuit of claim 17 , wherein the single charge pump is linearized during the linearization time period.
19. The PLL circuit of claim 16 , wherein the memorization circuit is further configured to copy the source current during a recopy time period in order to reduce noise.
20. The PLL circuit of claim 16 , wherein a length of the linearization time period is constant.
21. The PLL circuit of claim 16 , wherein a length of the linearization time period is proportional to a VCO period.