Semiconductor device generating internal clock signal having higher frequency than that of input clock signal

1. A device comprising:

a plurality of delay circuits connected in series, the delay circuits including an input-stage delay circuit receiving an input clock signal and an output-stage delay circuit outputting an output clock signal, each of the delay circuits representing a delay amount responsive to an operating voltage supplied thereto;

a regulator circuit controlling the operating voltage to be supplied to each of the delay circuits in response to a phase relationship between the input clock signal and the output clock signal; and

a synthesizing circuit configured to synthesize an internal clock signal based on clock signals supplied to selected ones of the delay circuits.

2. The device as claimed in claim 1 , wherein the delay circuits have the same circuit configuration as one another.

3. The device as claimed in claim 2 , wherein each of the delay circuits includes even stages of inverter circuits connected in series.

4. The device as claimed in claim 1 , wherein the regulator circuit increases the operating voltage when the output clock signal has a first logic level at a timing when the input clock signal changes from the first logic level to a second logic level, and decreases the operating voltage when the output clock signal has the second logic level at a timing when the input clock signal changes from the first logic level to the second logic level.

5. The device as claimed in claim 4 , further comprising a reference-edge detection circuit that decreases the operating voltage when a delay amount of the delay circuits exceeds a predetermined cycle that is longer than one cycle of the input clock signal.

6. The device as claimed in claim 1 , wherein the synthesis circuit inverts a logic level of the internal clock signal each time logic levels of the clock signals supplied to the selected ones of the delay circuits change.

7. The device as claimed in claim 6 , wherein the synthesis circuit changes the internal clock signal from a third logic level to a fourth logic level when clock signals supplied to even-numbered ones of the selected ones of the delay circuits change from a first logic level to a second logic level, and changes the internal clock signal from the fourth logic level to the third logic level when clock signals supplied to odd-numbered ones of the selected ones of the delay circuits change from the first logic level to the second logic level.

8. The device as claimed in claim 1 , further comprising:

a memory cell array including a plurality of memory cells; and

a peripheral circuit unit controlling an operation of the memory cell array,

wherein the memory cell array operates synchronously with the input clock signal and the peripheral circuit unit operates synchronously with the internal clock signal in a predetermined test mode.

9. The device as claimed in claim 1 , further comprising a DLL circuit that controls a phase of the input clock signal.

10. The device as claimed in claim 9 , further comprising a frequency division circuit that generates a frequency-divided clock signal by frequency-dividing an external clock signal supplied from outside the device,

wherein the DLL circuit generates the input clock signal by delaying the frequency-divided clock signal.

11. A method comprising:

electrically connecting N delay circuits in series, N being two or more integers;

controlling a level of an operating voltage to be supplied to each of the delay circuits so that a delay amount of each of the delay circuits becomes 1/N of a cycle of an input clock signal supplied to a leading one of the delay circuits; and

responding to signals to be respectively delayed by the delay circuits to generate an internal clock signal having a frequency that is N/2 times as large as the input clock signal.

12. The method as claimed in claim 11 , wherein the electrically connecting comprises connecting even numbers of inverter circuits in series to provide each of the delay circuits.

13. A device comprising:

a plurality of delay circuits each including an input node, an output node, a first power node and a second power node, the delay circuits being coupled in series such that the output node of a preceding one of the delay circuits is coupled to the input node of the succeeding one of the delay circuits, the input node of a leading one of the delay circuits receiving a first clock signal, the output node of a last one of the delay circuits producing a second clock signal, the first power node of each of the delay circuits being connected to a first power line, and the second power node of each of the delay circuits being connected to a second power line; and

a control circuit coupled to receive the first and second clock signals to control an operating voltage supplied between the first and second power lines.

14. The device as claimed in claim 13 , wherein the control circuit comprises a phase discrimination circuit that discriminates a phase difference between the first and second clock signal and a voltage circuit that responds an output signal of the phase discrimination circuit to vary the operating voltage.

15. The device as claimed in claim 13 , further comprising a synthesizing circuit coupled to the input node of each of the delay circuits to produce at an output terminal thereof a third clock signal that is greater in frequency than each of the first and second clock signals.

16. The device as claimed in claim 13 , wherein each of the delay circuit comprises N pieces of inverters, N being an even number.

17. The device as claimed in claim 16 , wherein each of the inverters comprising a first transistor of a first channel type and a second transistor of a second channel type that are connected in series between the first and second power nodes.

18. The device as claimed in claim 15 , wherein the synthesizing circuit comprises a first transistor connected between a first potential line and the output terminal, a second transistor connected between a second potential line and the output terminal, a first driver coupled to the input node of each of odd-numbered ones of the delay circuits to drive the first transistor, and a second driver coupled to the input node of each of even-numbered ones of the delay circuits to drive the second transistor.

19. The device as claimed in claim 13 , wherein a number of the delay circuits is even.

20. The device as claimed in claim 19 , wherein the number of delay circuits is even and is four or more.