IP Library Granted Patent US 9,547,320
Granted Patent B2
US 9,547,320 · App. 13/962,309 · Granted Jan 17, 2017

Power supply circuit and power supply apparatus

Inventor: Tadahiro Imada (Kawasaki, JP)
Assignee: FUJITSU LIMITED
G05F1/46H01L29/7787H02M3/24H01L29/2003H01L29/402H01L29/42316
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Quick Facts
Patent No.
US 9,547,320
App. No.
13/962,309
Granted
Jan 17, 2017
Kind
B2
Abstract

A power supply circuit includes: a depression mode transistor that includes a field plate; an enhancement mode transistor to which a source electrode and a drain electrode of the depression mode transistor are coupled; and a constant current source that is coupled to a connection node between the depression mode transistor and the enhancement mode transistor.

Claims (17)

1. A power supply circuit, comprising:

a depression mode transistor that includes a field plate;

an enhancement mode transistor to which a drain electrode and a source electrode of the depression mode transistor are coupled; and

a constant current source that is coupled to a connection node between the depression mode transistor and the enhancement mode transistor.

2. The power supply circuit according to claim 1 ,

wherein the depression mode transistor is formed of a compound semiconductor device including nitrogen.

3. The power supply circuit according to claim 1 ,

wherein the field plate is a source field plate coupled to the source electrode of the depression mode transistor.

4. The power supply circuit according to claim 1 ,

wherein the constant current source flows a current of 1×10 −11 to 1×10 −2 of a rated current of the depression mode transistor.

5. A power supply apparatus, comprising:

a DC-DC converter; and

a power supply circuit configured to supply power to the DC-DC converter,

wherein the power supply circuit includes

a depression mode transistor that includes a field plate,

an enhancement mode transistor to which a drain electrode and a source electrode of the depression mode transistor are coupled, and

a constant current source that is coupled to a connection node between the depression mode transistor and the enhancement mode transistor.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2013
From: IMADA, TADAHIRO
To: FUJITSU LIMITED
Reel/Frame 031103/0106 →
Priority Claims (1)
JP 2012-207252 · Sep 20, 2012 · national
Continuity (1)
Related Publication 20140078781A1 · Mar 20, 2014