Digital phase locked loop with feedback loops
Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.
1. A digital phase locked loop comprising:
a time-to-digital converter (TDC) configured to receive an input reference clock signal to produce a first digital feedback signal;
an adder configured to add said first digital feedback signal from a first feedback loop and a second digital feedback signal from a second feedback loop and produce a digital adder output;
a digitally controlled oscillator (DCO) configured to receive said digital adder output and produce a DCO output clock signal, said DCO output clock signal being locked in phase to said input reference clock signal.
2. The digital phase locked loop of claim 1 , further comprising a calibration circuit coupled to said first feedback loop and configured to calibrate a TDC signal provided by said TDC.
3. The digital phase locked loop of claim 1 , further comprising a calibration circuit coupled to said second feedback loop and configured to calibrate a TDC signal provided by said TDC.
4. The digital phase locked loop of claim 1 , further comprising a calibration circuit coupled to a conversion circuit to cause a first phase error from said first feedback loop and a second phase error from said second feedback to have a same unit.
5. The digital phase locked loop of claim 4 , wherein said conversion circuit includes a multiplication circuit.
6. The digital phase locked loop of claim 4 , wherein said conversion circuit is coupled to said second feedback loop.
7. The digital phase locked loop of claim 4 , wherein said conversion circuit includes a division circuit.
8. The digital phase locked loop of claim 4 , wherein said conversion circuit is coupled to said first feedback loop.
9. The digital phase locked loop of claim 1 , wherein said first and second feedback loops share a sampling circuit configured to sample said input reference clock signal at a clock rate of said DCO output clock signal.
10. The digital phase locked loop of claim 9 , further comprising a supervisor circuit configured to adjust a timing of a sampling at said sampling circuit.
11. The digital phase locked loop of claim 1 , wherein said second feedback loop includes a digital comparison circuit configured to produce a frequency error signal.
12. The digital phase locked loop of claim 11 , wherein said frequency error signal is indicative of a frequency difference between a desired clock signal and said DCO output clock signal.
13. The digital phase locked loop of claim 1 , further comprising a digital integrator configured to convert a frequency difference between a desired frequency and a generated frequency of said DCO output clock signal into said second digital feedback signal.
14. The digital phase locked loop of claim 1 , further comprising a loop filter.
15. The digital phase locked loop of claim 1 , further comprising a dither circuit coupled between said adder and said DCO.
16. A digital phase locked loop comprising:
a time-to-digital converter (TDC) configured to receive an input reference clock signal;
a calibration circuit coupled to a first feedback loop and configured to calibrate a TDC signal provided by said TDC;
a digitally controlled oscillator (DCO) configured to produce a DCO output clock signal, said DCO output clock signal being locked in phase to said input reference clock signal.
17. The digital phase locked loop of claim 16 , further comprising a calibration circuit coupled to a second feedback loop and configured to calibrate said TDC signal.
18. The digital phase locked loop of claim 17 , wherein said first and second feedback loops share a sampling circuit configured to sample said input reference clock signal at a clock rate of said DCO output clock signal.
19. The digital phase locked loop of claim 18 , further comprising a supervisor circuit configured to adjust a timing of a sampling at said sampling circuit.
20. The digital phase locked loop of claim 16 , further comprising a loop filter.