IP Library Granted Patent US 9,065,696
Granted Patent B2
US 9,065,696 · App. 13/969,534 · Granted Jun 23, 2015

Adaptive equalizer

Inventors: Georgios Asmanis (Lake Forest, CA); Faouzi Chaahoub (San Jose, CA); Samir Aboulhouda (Cupertino, CA); Sriramkumar Sundararaman (Belmont, CA); Ajay Kumar Yadav (Belmont, CA)
Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
H04L25/03006
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Quick Facts
Patent No.
US 9,065,696
App. No.
13/969,534
Granted
Jun 23, 2015
Kind
B2
Abstract

An equalizer that includes equalizer circuitry, a mean squared error (MSE) system, and adaptive control logic includes features that inhibit undesirable convergence to local minima.

Claims (42)

1. An equalizer, comprising:

equalizer circuitry configured to output an equalized signal in response to an input signal, a plurality of gain control signals, and a plurality of dither control signals, the equalizer circuitry having a plurality of taps, each tap controlled by a set of control signals comprising one of the plurality of gain control signals and one of the plurality of dither control signals;

a mean squared error (MSE) system configured to provide an output MSE value in response to the equalized signal during each of a plurality of cycles; and

adaptive control logic configured to adjust the plurality of gain control signals and the plurality of dither control signals in response to an MSE value, the adaptive control logic configured to select the plurality of taps in a predetermined sequence over the plurality of cycles, wherein the adaptive control logic is configured to determine whether the output MSE value is less than a best MSE value following adjustment of the set of control signals controlling a selected tap during one of the plurality of cycles, the adaptive control logic further configured to set the best MSE value to the output MSE value and to adjust a gain control signal controlling the selected tap during a cycle if it is determined that the output MSE value is less than the best MSE value, and wherein if the adaptive control logic determines that the output MSE value is less than the best MSE value following adjustment of the set of control signals controlling a selected tap, then before selecting a next tap of the plurality of taps in the predetermined sequence during a next cycle the adaptive control logic adjusts the dither control signal to a different dither value and determines whether the output MSE value in response to the different dither value is less than the best MSE value, wherein the adaptive control logic is further configured to iteratively adjust a limiting path signal swing in the MSE system and determine whether adjusting the limiting path signal swing results in a decrease in an amplitude difference between a limiting path signal and a linear path signal in the MSE system.

2. The equalizer of claim 1 , wherein the adaptive control logic is further configured to determine if the best MSE value is substantially equal to the output MSE value after a predetermined number of sequential cycles, the adaptive control logic setting the best MSE value to the output MSE value if it is determined that the best MSE value is substantially equal to the output MSE value after the predetermined number of sequential cycles.

3. The equalizer of claim 1 , wherein if the adaptive control logic determines that the output MSE value is less than the best MSE value following adjustment of the set of control signals controlling a selected tap, then before selecting a next tap of the plurality of taps and before adjusting the dither control signal the adaptive control logic adjusts the gain control signal controlling the selected tap to a different gain value and determines whether the output MSE value in response to the different gain value is less than the best MSE value.

4. The equalizer of claim 1 , wherein the adaptive control logic is further configured to iteratively adjust a gain input signal provided to the MSE system and to determine whether adjusting the gain input signal results in an increase in the output MSE value.

5. The equalizer of claim 1 , wherein the adaptive control logic is further configured to iteratively adjust a continuous time linear equalizer (CTLE) input signal provided to the equalizer circuitry and to determine whether adjusting the CTLE input signal results in a decrease in the output MSE value.

6. The equalizer of claim 1 , wherein the predetermined sequence is user-selectable.

7. The equalizer of claim 1 , wherein the adaptive control logic is configured to iteratively adjust the gain control signal controlling the selected tap to a different gain value while maintaining dither control signal controlling the selected tap at the same dither value without selecting the next tap on each of a plurality of iterations, until the adaptive control logic determines that the output MSE value is not less than the best MSE value following adjustment of the set of control signals controlling a selected tap.

8. The equalizer of claim 1 , wherein the adaptive control logic directs the equalizer circuitry to provide an equalized signal responsive to a summing node and a slicer.

9. The equalizer of claim 2 , wherein the adaptive control logic is further configured to iteratively determine if the best MSE value is substantially equal to the output MSE value after a predetermined number of sequential cycles in each of a plurality of iterations, the adaptive control logic setting circuitry to a low power consumption mode if it is determined that the best MSE value is substantially equal to the output MSE value after a predetermined number of sequential cycles in each of a plurality of iterations.

10. A method of operation in an equalizer comprising equalizer circuitry, a mean squared error (MSE) system, and adaptive control logic, the method comprising:

the equalizer circuitry outputting an equalized signal in response to an input signal, a plurality of gain control signals, and a plurality of dither control signals, the equalizer circuitry having a plurality of taps, each tap controlled by a set of control signals comprising one of the plurality of gain control signals and one of the plurality of dither control signals;

the MSE system providing an output MSE value in response to the equalized signal during each of a plurality of cycles;

the adaptive control logic adjusting the plurality of gain control signals and the plurality of dither control signals in response to an MSE value, the adaptive control logic selecting the plurality of taps in a predetermined sequence over the plurality of cycles including selecting a next tap during a next cycle;

the adaptive control logic determining whether the output MSE value is less than a best MSE value following adjustment of the set of control signals controlling a selected tap during one of the plurality of cycles;

the adaptive control logic setting the best MSE value to the output MSE value and adjusting a gain control signal controlling the selected tap during a cycle if the adaptive control logic determines that the output MSE value is less than the best MSE value; and

before selecting a next tap, if the adaptive control logic determines that the output MSE value is less than the best MSE value following adjustment of the set of control signals controlling a selected tap, then the adaptive control logic adjusting the dither control signal to a different dither value and determines whether the output MSE value in response to the different dither value is less than the best MSE value, the adaptive control logic iteratively adjusting a limiting path signal swing in the MSE system and determining whether adjusting the limiting path signal swing results in a decrease in an amplitude difference between a limiting path signal and a linear path signal in the MSE system.

11. The method of claim 10 , further comprising:

the adaptive control logic determining if the best MSE value is substantially equal to the output MSE value after a predetermined number of sequential cycles; and

the adaptive control logic setting the best MSE value to the output MSE value if it is determined that the MSE value is substantially equal to the output MSE value after the predetermined number of sequential cycles.

12. The method of claim 10 , further comprising:

if the adaptive control logic determines that the output MSE value is less than the best MSE value following adjustment of the set of control signals controlling a selected tap, then before selecting a next tap of the plurality of taps and before adjusting the dither control signal the adaptive control logic adjusts the gain control signal controlling the selected tap to a different gain value and determines whether the output MSE value in response to the different gain value is less than the best MSE value.

13. The method of claim 10 , further comprising the adaptive control logic iteratively adjusting a gain input signal provided to the MSE system and determining whether adjusting the gain input signal results in an increase in the output MSE value.

14. The method of claim 10 , further comprising the adaptive control logic iteratively adjusting a continuous time linear equalizer (CTLE) input signal provided to the equalizer circuitry and determining whether adjusting the CTLE input signal results in a decrease in output MSE value.

15. The method of claim 10 , further comprising the adaptive control logic receiving user input indicating a user's selection of the predetermined sequence.

16. The method of claim 10 , further comprising the adaptive control logic iteratively adjusting the gain control signal controlling the selected tap to a different gain value while maintaining dither control signal controlling the selected tap at the same dither value without selecting the next tap on each of a plurality of iterations, until the adaptive control logic determines that the output MSE value is not less than the best MSE value following adjustment of the set of control signals controlling a selected tap.

17. The method of claim 10 , further comprising the adaptive control logic iteratively adjusting a decision feedback equalizer (DFE) input signal provided to the equalizer circuitry and generating an equalized signal responsive to a summing node and a slicer.

18. The method of claim 11 , further comprising:

the adaptive control logic iteratively determining if the best MSE value is substantially equal to the output MSE value after a predetermined number of sequential cycles in each of a plurality of iterations; and

the adaptive control logic setting circuitry to a low power consumption mode if it is determined that the best MSE value is substantially equal to the output MSE value after a predetermined number of sequential cycles in each of a plurality of iterations.

19. A computer program product for controlling a system comprising equalizer circuitry, a mean squared error (MSE) system, and adaptive control logic, the adaptive control logic comprising a processor, the computer program product comprising a non-transitory computer-readable medium having stored thereon in computer-executable format instructions that when executed on the processor cause the processor to effect a method comprising:

the equalizer circuitry outputting an equalized signal in response to an input signal, a plurality of gain control signals, and a plurality of dither control signals, the equalizer circuitry having a plurality of taps, each tap controlled by a set of control signals comprising one of the plurality of gain control signals and one of the plurality of dither control signals;

the MSE system providing an output MSE value in response to the equalized signal during each of a plurality of cycles;

the adaptive control logic adjusting the plurality of gain control signals and the plurality of dither control signals in response to an MSE value, the adaptive control logic selecting the plurality of taps in a predetermined sequence over the plurality of cycles including selecting a next tap during a next cycle;

the adaptive control logic determining whether the output MSE value is less than a best MSE value following adjustment of the set of control signals controlling a selected tap during one of the plurality of cycles;

the adaptive control logic setting the best MSE value to the output MSE value and adjusting a gain control signal controlling the selected tap during a cycle if the adaptive control logic determines that the output MSE value is less than the best MSE value; and

before selecting a next tap, if the adaptive control logic determines that the output MSE value is less than the best MSE value following adjustment of the set of control signals controlling a selected tap, then the adaptive control logic adjusting the dither control signal to a different dither value and determines whether the output MSE value in response to the different dither value is less than the best MSE value, the adaptive control logic iteratively adjusting a limiting path signal swing in the MSE system and determining whether adjusting the limiting path signal swing results in a decrease in an amplitude difference between a limiting path signal and a linear path signal in the MSE system.

20. The computer program product of claim 19 , wherein the method effected by execution of the instructions further comprises:

the adaptive control logic determining if the best MSE value is substantially equal to the output MSE value after a predetermined number of sequential cycles; and

the adaptive control logic setting the best MSE value to the output MSE value if it is determined that the MSE value is substantially equal to the output MSE value after the predetermined number of sequential cycles.

Assignments (9)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2013
From: ASMANIS, GEORGIOS; CHAAHOUB, FAOUZI; ABOULHOUDA, SAMIR; SUNDARARAMAN, SRIRAMKUMAR; YADAV, AJAY KUMAR
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 031032/0177 →
Continuity (1)
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