System and method for high speed data parallelization for an N-phase receiver
A serial-to-parallel converter includes a first register bank having first and second register groups, the first register bank configured to receive a communication signal having at least one bit for each unit interval (UI) of a system clock signal, the first register bank having a number of registers corresponding to a number of parallel processing stages, a second register bank having a plurality of register groups, each register group configured to receive the output of at least one of the first and second register groups after a number of unit intervals corresponding to the number of registers in each of the first and second register groups in the first register bank, and a third register bank configured to receive the output of the second register bank after a number of unit intervals corresponding to a number of registers in the second register bank.
1. A serial-to-parallel converter, comprising:
a first register bank having first and second register groups, the first register bank configured to receive a communication signal having at least one bit for each unit interval (UI) of a system clock signal, the first register bank having a number of registers corresponding to a number of parallel processing stages;
a second register bank having a plurality of register groups, each register group configured to receive the output of at least one of the first and second register groups after a number of unit intervals corresponding to the number of registers in each of the first and second register groups in the first register bank; and
a third register bank configured to receive the output of the second register bank after a number of unit intervals corresponding to a number of registers in the second register bank.
2. The serial-to-parallel converter of claim 1 , further comprising eight (8) parallel processing stages, wherein an input clock signal corresponds to an F8 clock speed.
3. The serial-to-parallel converter of claim 2 , wherein an output of the third register bank is a 20 bit word corresponding to an F20 clock speed.
4. The serial-to-parallel converter of claim 3 , wherein the first register bank comprises eight (8) registers.
5. The serial-to-parallel converter of claim 3 , wherein the second register bank comprises five (5) groups of four (4) registers.
6. The serial-to-parallel converter of claim 3 , wherein the third register bank comprises twenty (20) registers.
7. The serial-to-parallel converter of claim 3 , wherein a first register group of the second register bank is loaded with the contents of at least one of the first and second register groups of the first register bank on the same clock cycle during which the third register bank is loaded with the contents of the five (5) groups of four (4) registers of the second register bank.
8. The serial-to-parallel converter of claim 3 , further comprising a fourth register bank arranged in a one hot configuration, the fourth register bank comprising five registers, one of which causes the output of at least one of the first and second register groups to be sequentially loaded into a register group of the second register bank.
9. The serial-to-parallel converter of claim 8 , wherein the fourth register bank comprises one register for each register group in the second register bank.
10. A method for serial-to-parallel conversion, comprising:
loading data sequentially into a first register bank at a speed corresponding to an F8 clock;
every four clock cycles, loading four bits of data from the first register bank into one of five register groups of a second register bank;
every fourth clock cycle, loading four bits of data into a successive register group of the second register bank until the five register groups are loaded with twenty (20) bits of data; and
loading the twenty (20) bits of data into a third register bank having one (1) group of twenty (20) registers, the twenty (20) bits of data loaded into the third register bank at a speed corresponding to an F20 clock.
11. The method of claim 10 , wherein loading data sequentially into the first register bank comprises loading the data into eight registers over eight clock cycles.
12. The method of claim 11 , further comprising implementing each of the five register groups of the second register bank using four (4) registers.
13. The method of claim 12 , further comprising loading a first register group of the second register bank with the contents of at least one of the first and second register groups of the first register bank on the same clock cycle during which the third register bank is loaded with the contents of the five (5) groups of four (4) registers of the second register bank.
14. The method of claim 13 , further comprising implementing a fourth register bank in a one hot configuration, the fourth register bank comprising five registers, each register in the fourth register group corresponding to one register group in the second register bank, one register of the fourth register group causing the output of at least one of the first and second register groups to be sequentially loaded into a register group of the second register bank.
15. A receiver having parallel processing stages, comprising:
a plurality of equalizers having parallel processing stages, the plurality of equalizers configured to process a received data signal and develop a communication signal having a plurality of data bits each data bit separated in time by one unit interval of a system clock;
a serial-to-parallel converter configured to receive the communication signal, the serial-to-parallel converter comprising;
a first register bank having first and second register groups, the first register bank configured to receive the communication signal the first register bank having a number of registers corresponding to the number of parallel processing stages;
a second register bank having a plurality of register groups, each register group configured to receive the output of the first and second register groups after a number of unit intervals corresponding to the number of registers in each of the first and second register groups in the first register bank; and
a third register bank configured to receive the output of the second register bank after a number of unit intervals corresponding to the size of the second register bank.
16. The receiver of claim 15 , further comprising eight (8) parallel processing stages, wherein an input clock signal corresponds to an F8 clock speed.
17. The receiver of claim 16 , wherein an output of the third register bank is a 20 bit word corresponding to an F20 clock speed.
18. The receiver of claim 17 , wherein the first register bank comprises eight (8) registers.
19. The receiver of claim 17 , wherein the second register bank comprises five (5) groups of four (4) registers.
20. The receiver of claim 17 , wherein the third register bank comprises twenty (20) registers.
21. The receiver of claim 17 , wherein a first register group of the second register bank is loaded with the contents of at least one of the first and second register groups of the first register bank on the same clock cycle during which the third register bank is loaded with the contents of the five (5) groups of four (4) registers of the second register bank.
22. The receiver of claim 17 , further comprising a fourth register bank arranged in a one hot configuration, the fourth register bank comprising five registers, one of which causes the output of at least one of the first and second register groups to be sequentially loaded into a register group of the second register bank.
23. The receiver of claim 22 , wherein the fourth register bank comprises one register for each register group in the second register bank.