Method and apparatus for eliminating shimmering

1. An integrated circuit, comprising:

a switch control circuit configured to provide a control signal to enable/disable a first pulse width modulation (PWM) signal for driving a first regulator to transfer power to a first load and to enable/disable a second PWM signal to a second regulator to transfer power to a second load; and

a timing control circuit configured to disable an analog to digital converter (ADC) from converting an analog signal to a digital stream in response to the switch control circuit enabling the first PWM signal and the second PWM signal, and to enable the ADC to convert the analog signal to the digital stream when the first PWM signal and the second PWM signal are disabled in order to reduce noise in the digital stream due to switching activities in the first regulator and the second regulator.

2. The integrated circuit of claim 1 , wherein the switch control circuit is configured to generate the control signal with a duty cycle determined according to a digital value in the digital stream and to use the control signal to enable/disable the first and second PWM signals.

3. The integrated circuit of claim 2 , wherein the switch control circuit is configured to generate the control signal with the duty cycle determined according to an average of a plurality of digital values in the digital stream.

4. The integrated circuit of claim 2 , wherein the switch control circuit comprises:

a duty cycle determination module configured to determine the duty cycle according to a control value; and

a noise rejection module configured to reject a new digital value when a difference of the new digital value to the control value is within a range.

5. The integrated circuit of claim 4 , wherein the switch control circuit further comprises:

an averaging module configured to average a plurality of digital values not being rejected to calculate a new control value.

6. The integrated circuit of claim 1 , wherein the switch control circuit is configured to generate a first control signal with a first duty cycle to enable/disable the first PWM signal and a second control signal with a second duty cycle to enable/disable the second PWM signal, and the first duty cycle and the second duty cycle are determined according to a digital value in the digital stream.

7. The integrated circuit of claim 6 , wherein the switch control circuit is configured to generate the first control signal and the second control signal with at least a pair of aligned transition edges.

8. A method, comprising:

enabling first pulse width modulation (PWM) signal that drives a first regulator that transfers power to a first load and enabling a second PWM signal to a second regulator to transfer power to a second load;

disabling the first PWM signal to the first regulator periodically and disabling the second PWM signal to the second regulator periodically; and

converting an analog signal to a digital stream in response to disabling of the first and second PWM signals in order to reduce noise in the digital stream due to switching activities in the first regulator and the second regulator.

9. The method of claim 8 , further comprising:

generating a control signal with a duty cycle determined according to a digital value in the digital stream; and

using the control signal to enable/disable the first and second PWM switch signals.

10. The method of claim 9 , further comprising:

computing an average of a plurality of digital values in the digital stream; and

generating the control signal with the duty cycle determined according to the average.

11. The method of claim 9 , further comprising:

rejecting a new digital value when a difference of the new digital value to a control value is within a range.

12. The method of claim 11 , further comprising:

computing the control value as an average of a plurality of digital values that are not rejected; and

generating the control signal with the duty cycle determined according to the control value.

13. The method of claim 8 , further comprising at least one of:

enabling the first PWM signal and the second PWM signal at a some time; and

disabling the first PWM signal and the second PWM signal at a same time.

14. An apparatus, comprising:

a first regulator configured to transfer power to a first load when a first pulse width modulation (PWM) signal that drives the first regulator is enabled;

a second regulator configured to transfer power to a second load when a second pulse width modulation (PWM) signal that drives the second regulator is enabled;

a switch control circuit configured to enable/disable the first PWM signal to the regulator and to enable/disable the second PWM to the second regulator to transfer power to a second load; and

a timing control circuit configured to disable an analog to digital converter (ADC) from converting an analog signal to a digital stream in response to the switch control circuit enabling the first PWM signal and the second PWM signal, and configured to enable the ADC to convert the analog signal to the digital stream when the first PWM signal and the second PWM signal are disabled in order to reduce noise in the digital stream due to switching activities in the first regulator and the second regulator.

15. The apparatus of claim 14 , wherein the switch control circuit is configured to generate a control signal with a duty cycle determined according to a value in the digital stream and to use the control signal to enable/disable the first PWM signal and the second PWM signal.

16. The apparatus of claim 15 , wherein the switch control circuit is configured to generate the control signal with the duty cycle determined according to an average of a plurality of digital values in the digital stream.

17. The apparatus of claim 15 , wherein the switch control circuit comprises:

a duty cycle determination module configured to determine the duty cycle according to a control value; and

a noise rejection signal configured to reject a new digital value when a difference of the new digital value to the control value within a range.

18. The apparatus of claim 17 , wherein the switch control circuit further comprises:

an averaging module configured to average a plurality of digital values not being rejected to calculate a new control value.