Semiconductor device with buffer and replica circuits
View Patent ↗A semiconductor device includes a first input buffer adjusting a logic threshold voltage, a first replica circuit, a first reference voltage generating circuit, and a first comparator circuit. The first replica circuit is identical in circuit configuration to the first input buffer. The first replica circuit has an input and an output connected to the input. The first replica circuit generates the logic threshold voltage as an output voltage. The first reference voltage generating circuit generates a first reference voltage. The first comparator circuit compares the logic threshold voltage as an output voltage of the first replica circuit to the first reference voltage to generate a first threshold adjustment signal. The first comparator circuit supplies the first threshold adjustment signal to the first input buffer and the first replica circuit. The first threshold adjustment signal allows the first input buffer to adjust the logic threshold voltage.
1. A semiconductor device, comprising:
an input buffer comprising:
first and second PMOS transistors serially interconnected between a first power supply node and an output node of the input buffer; and
first and second NMOS transistors serially interconnected between a second power supply node and the output node of the input buffer,
wherein a gate of the first PMOS transistor and a gate of the first NMOS transistor are connected to an input node of the input buffer, and a gate of the second PMOS transistor is connected to a gate of the second NMOS transistor;
a replica circuit comprising:
third and fourth PMOS transistors serially interconnected between the first power supply node and an output node of the replica circuit; and
third and fourth NMOS transistors serially interconnected between the second power supply node and the output node of the replica circuit,
wherein a gate of the third PMOS transistor is connected to a gate of the third NMOS transistor, a gate of the fourth PMOS transistor and a gate of the fourth NMOS transistor are connected to an input node of the replica circuit, and the input node of the replica circuit is connected to the output node of the replica circuit;
a reference voltage generating circuit comprising first and second resistors serially interconnected between the first power supply node and the second power supply node and providing a reference voltage at a node interconnecting the first and second resisters; and
a comparator circuit that compares a voltage at the output node of the replica circuit to the reference voltage of the reference voltage generating circuit, an output voltage of the comparator circuit being connected to the gates of the second PMOS transistor and second NMOS transistor and to the gates of the third PMOS transistor and third NMOS transistor.