Method of manufacturing semiconductor integrated circuit device
View Patent ↗A method of manufacturing a semiconductor integrated circuit device which includes a semiconductor substrate; and multiple semiconductor elements disposed on the semiconductor substrate. The semiconductor elements include an n-channel MOS transistor and a p-channel MOS transistor. The n-channel MOS transistor is covered by a tensile stress film, and the p-channel MOS transistor is covered by a compressive stress film. A dummy region, the entire surface of which is covered by a combination of the tensile stress film and the compressive stress film, is disposed on the surface of the semiconductor substrate.
1. A method of manufacturing a semiconductor integrated circuit device, comprising:
forming, over an entire surface of a semiconductor substrate, a tensile stress film having tensile stress in such a manner as to cover an n-channel MOS transistor and a p-channel MOS transistor;
forming a first resist film over the tensile stress film;
performing patterning on the first resist film to form a first resist aperture in the first resist film in such a manner as to correspond to first mask data which define an element region of the p-channel MOS transistor, and form, in an element isolating region provided on the semiconductor substrate, a second resist aperture in the first resist film in such a manner as to correspond to second mask data which define a dummy region;
selectively removing the tensile stress film from the first resist aperture and the second resist aperture so that the tensile stress film remaining over the n-channel MOS transistor serves as a tensile stress source pattern and the tensile stress film remaining in the element isolating region serves as a dummy pattern;
removing the first resist film and forming, over the entire surface of the semiconductor substrate, a compressive stress film having compressive stress;
forming a second resist film over the compressive stress film;
performing patterning on the second resist film to form a first resist pattern complementarily to the first resist aperture in such a manner that the element region of the p-channel MOS transistor remains covered by the second resist film and form a second resist pattern complementarily to the second resist aperture, the first resist pattern corresponding to the first mask data and the second resist pattern corresponding to the second mask data; and
performing patterning on the compressive stress film using the first resist pattern and the second resist pattern as masks so that the compressive stress film remaining over the p-channel MOS transistor serves as a compressive stress source pattern and the compressive stress film remaining in the element isolating region serves as a complementary dummy pattern which is complementary to the dummy pattern.
2. The method as claimed in claim 1 , wherein a ratio between a total area of the dummy pattern and a total area of the complementary dummy pattern is in a range of 3/7 to 7/3.
3. A method of manufacturing a semiconductor integrated circuit device, comprising:
forming, over an entire surface of a semiconductor substrate, a compressive stress film having compressive stress in such a manner as to cover an n-channel MOS transistor and a p-channel MOS transistor;
forming a first resist film over the compressive stress film;
performing patterning on the first resist film to form a first resist aperture in the first resist film in such a manner as to correspond to first mask data which define an element region of the n-channel MOS transistor, and form, in an element isolating region provided on the semiconductor substrate, a second resist aperture in the first resist film in such a manner as to correspond to second mask data which define a dummy region;
selectively removing the compressive stress film from the first resist aperture and the second resist aperture so that the compressive stress film remaining over the p-channel MOS transistor serves as a compressive stress source pattern and the compressive stress film remaining in the element isolating region serves as a dummy pattern;
removing the first resist film and forming, over the entire surface of the semiconductor substrate, a tensile stress film having tensile stress;
forming a second resist film over the tensile stress film;
performing patterning on the second resist film to form a first resist pattern complementarily to the first resist aperture in such a manner that the element region of the re-channel MOS transistor remains covered by the second resist film and form a second resist pattern complementarily to the second resist aperture, the first resist pattern corresponding to the first mask data and the second resist pattern corresponding to the second mask data; and
performing patterning on the tensile stress film using the first resist pattern and the second resist pattern as masks so that the tensile stress film remaining over the re-channel MOS transistor serves as a tensile stress source pattern and the tensile stress film remaining in the element isolating region serves as a complementary dummy pattern which is complementary to the dummy pattern.
4. The method as claimed in claim 3 , wherein a ratio between a total area of the dummy pattern and a total area of the complementary dummy pattern is in a range of 3/7 to 7/3.