Modal PAM2/4 Pipelined Programmable Receiver Having Feed Forward Equalizer (FFE) And Decision Feedback Equalizer (DFE) Optimized For Forward Error Correction (FEC) Bit Error Rate (BER) Performance
A pipelined receiver comprises a programmable feed forward equalizer (FFE), a programmable decision feedback equalizer (DFE), and logic for controlling a ratio of FFE and DFE to apply to a received signal based on at least one channel parameter.
1 . A pipelined receiver, comprising:
a programmable feed forward equalizer (FFE);
a programmable decision feedback equalizer (DFE); and
a logic element configured to control at least one of a number of FFE taps and DFE taps to apply to a received signal based on at least one channel parameter.
2 . The pipelined receiver of claim 1 , wherein the channel parameter is bit error rate (BER).
3 . The pipelined receiver of claim 1 , wherein the channel parameter is signal-to-noise ratio (SNR).
4 . The pipelined receiver claim 1 , further comprising a forward error correction (FEC) element, wherein the at least one of a number of FFE taps and DFE taps is controlled such that the available FFE is optimized.
5 . The pipelined receiver of claim 1 , wherein the at least one of a number of FFE taps and DFE taps is controlled such that the function of the FFE and the DFE overlap.
6 . The pipelined receiver of claim 1 , wherein a number of FFE taps, a gain applied to each FFE tap, a number of DFE taps, and a gain applied to each DFE tap are determined based on the at least one channel parameter.
7 . The pipelined receiver of claim 5 , wherein a number of FFE taps, a gain applied to each FFE tap, a number of DFE taps, and a gain applied to each DFE tap are determined based on the at least one channel parameter and are simultaneously applied to the at least one bit.
8 . A method for processing a signal in a pipelined receiver, comprising:
providing the receiver with a programmable feed forward equalizer (FFE);
providing a programmable decision feedback equalizer (DFE); and
controlling at least one of a number of FFE taps and DFE taps applied to a received signal based on at least one channel parameter.
9 . The method of claim 8 , wherein the channel parameter is bit error rate (BER).
10 . The method of claim 8 , wherein the channel parameter is signal-to-noise ratio (SNR).
11 . The method of claim 8 , further comprising:
providing a forward error correction (FEC) element; and
controlling the at least one of a number of FFE taps and DFE taps such that the available FFE is optimized.
12 . The method of claim 8 , further comprising controlling the at least one of a number of FFE taps and DFE taps such that the function of the FFE and the DFE overlap.
13 . The method of claim 8 , wherein a number of FFE taps, a gain applied to each FFE tap, a number of DFE taps, and a gain applied to each DFE tap are determined based on the at least one channel parameter.
14 . The method of claim 12 , wherein a number of FFE taps, a gain applied to each FFE tap, a number of DFE taps, and a gain applied to each DFE tap are determined based on the at least one channel parameter and are simultaneously applied to the at least one bit.
15 . A receiver system, comprising:
a plurality of parallel processing stages configured to receive an output of a continuous time linear equalizer (CTLE);
a programmable feed forward equalizer (FFE);
a programmable decision feedback equalizer (DFE); and
a logic element configured to control at least one of a number of FFE taps and DFE taps to apply to a received signal based on at least one channel parameter.
16 . The receiver system of claim 15 , wherein the channel parameter is bit error rate (BER).
17 . The receiver system of claim 15 , wherein the channel parameter is signal-to-noise ratio (SNR).
18 . The receiver system claim 15 , further comprising a forward error correction (FEC) element, wherein the at least one of number of FFE taps and DFE taps is controlled such that the available FFE is optimized.
19 . The receiver system of claim 15 , wherein the at least one of a number of FFE taps and DFE to taps is controlled such that the function of the FFE and the DFE overlap.
20 . The receiver system of claim 15 , wherein a number of FFE taps, a gain applied to each FFE tap, a number of DFE taps, and a gain applied to each DFE tap are determined based on the at least one channel parameter.
21 . The receiver system of claim 19 , wherein a number of FFE taps, a gain applied to each FFE tap, a number of DFE taps, and a gain applied to each DFE tap are determined based on the at least one channel parameter and are simultaneously applied to the at least one bit.