Method of fabricating printed circuit board (PCB) substrate having a cavity

1. A method of fabricating a substrate having a plurality of metal layers separated by one or more dielectric layers, the method comprising:

forming a cavity in at least one dielectric layer through an exposed portion of a top dielectric layer of the substrate;

applying metal to side and bottom surfaces of the cavity;

forming a pattern through a portion of the metal applied to the bottom surface of the cavity; and

micro-etching the metal applied to the bottom surface of the cavity, the micro-etching extending the pattern through a remaining portion of the metal applied to the bottom surface of the cavity.

2. The method of claim 1 , wherein applying the metal to the side and bottom surfaces of the cavity comprises performing a metal plating operation.

3. The method of claim 2 , wherein the metal applied to the side and bottom surfaces of the cavity is configured to provide EMI shield from adjacent circuitry.

4. The method of claim 1 , further comprising:

applying a photoresist pattern over a top metal layer of the plurality of metal layers before applying the metal to the side and bottom surfaces of the cavity, the photoresist pattern defining an opening over the exposed portion of the top dielectric layer; and

removing the photoresist pattern after micro-etching the bottom surface of the cavity.

5. The method of claim 1 , wherein the metal layers and the metal applied to the side and bottom surfaces of the cavity are formed of copper.

6. The method of claim 5 , wherein the dielectric layers are formed of glass reinforced epoxy material.

7. The method of claim 6 , wherein the glass reinforced epoxy material comprises FR-4 material.

8. The method of claim 5 , wherein the dielectric layers are formed of non-glass reinforced epoxy material.

9. The method of claim 5 , wherein the dielectric layers are formed of glass reinforced polymer material.

10. The method of claim 5 , wherein the dielectric layers are formed of non-glass reinforced polymer material.

11. The method of claim 1 , wherein the cavity is formed in the at least one dielectric layer using laser ablation.

12. The method of claim 11 , wherein the laser ablation is performed by a CO 2 laser.

13. The method of claim 1 , wherein the pattern is formed through the portion of the metal applied to the bottom surface of the cavity using laser ablation.

14. The method of claim 13 , wherein the laser ablation is performed by a UV laser.

15. The method of claim 1 , wherein the cavity is configured to expose PCB circuitry for flip-chip or die-attach assembly of a semiconductor, enabling reduced thermal resistance and reducing overmold thickness.

16. A method of fabricating a substrate, comprising:

forming a plurality of metal layers separated by one or more dielectric layers, a top metal layer of the plurality of metal layers defining a first opening that exposes a portion of a top dielectric layer of the plurality of dielectric layers;

applying a photoresist pattern over the top metal layer, the photoresist pattern defining a second opening over the first opening in the top metal layer;

ablating the top dielectric layer using a first laser through the first and second openings to form a cavity through at least the top dielectric layer;

plating metal to side and bottom surfaces of the cavity;

ablating the plated metal on the bottom surface of the cavity using a second laser to form a pattern through a portion of the plated metal on the bottom surface of the cavity; and

micro-etching the plated metal on the bottom surface of the cavity to extend the pattern through a remaining portion of the plated metal applied to the bottom surface of the cavity.

17. The method of claim 16 , wherein the first laser is a CO 2 laser and the second laser is a UV laser.

18. The method of claim 16 , wherein the portion of the plated metal on the bottom surface of the cavity through which the pattern is formed is a majority of a thickness of the plated metal on the bottom surface.

19. The method of claim 16 , wherein the micro-etching is performed using a wet chemistry.

20. The method of claim 16 , wherein the metal plated to the side and bottom surfaces of the cavity is configured to provide EMI shield from adjacent circuitry.