IP Library Granted Patent US 9,112,463
Granted Patent B2
US 9,112,463 · App. 14/041,414 · Granted Aug 18, 2015

Pulsed dynamic load modulation power amplifier circuit

Inventors: Moon-Suk Jeon (Seoul, KR); Jung-Rin Woo (Seoul, KR); Sung-Hwan Park (Seoul, KR); Jung Hyun Kim (Uiwang, KR); Young Kwon (Thousand Oaks, CA)
H03G3/00H03F3/191
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Quick Facts
Patent No.
US 9,112,463
App. No.
14/041,414
Granted
Aug 18, 2015
Kind
B2
Abstract

A power amplifier circuit for amplifying an envelope modulated Radio Frequency (RF) signal with improved linearity and efficiency includes a power amplifier, and a variable load matching circuit coupled to an output port of the power amplifier. The input impedance of the variable load matching circuit is changed such that an output power of the power amplifier is at a first output power level, or a second output power level which is higher than the first output power level.

Claims (41)

1. A power amplifier circuit, comprising:

a power amplifier configured to amplify an envelope modulated radio frequency (RF) signal; and

a variable load matching circuit coupled to an output port of the power amplifier, the variable load matching circuit configured to have an input impedance that is changeable so that an output power of the power amplifier changes between a first output power level and a second output power level which is higher than the first output power level, wherein the variable load matching circuit is configured to change the input impedance depending on a pulse width of a pulse width modulation (PWM) signal; and

a band-pass filter coupled to an output port of the variable load matching circuit, wherein an output power of the band-pass filter changes responsive to the input impedance of the variable load matching circuit.

2. The power amplifier circuit of claim 1 , wherein the variable load matching circuit is configured so that the input impedance is high when the output power of the power amplifier is at the first output power level and low when the output power of the power amplifier is at the second output power level.

3. The power amplifier circuit of claim 1 , wherein the variable load matching circuit comprises a shunt capacitor and a switch configured to switch the shunt capacitor.

4. The power amplifier circuit of claim 1 , further comprising a pulse width modulation (PWM) signal generator configured to generate a PWM signal, wherein the input impedance of the variable load matching circuit is switched based on the PWM signal.

5. A method of amplifying an envelope modulated Radio Frequency (RF) signal using a power amplifier, comprising:

changing an impedance coupled to an output port of the power amplifier, so that an output power of the power amplifier changes between a first output power level and a second output power level, which is higher than the first output power level, wherein the impedance coupled to the input port of the power amplifier is changed based on a pulse width modulation signal; and

changing an impedance coupled to an input port of the power amplifier so that the power amplifier operates in a saturation region.

6. The method of claim 5 , wherein the impedance coupled to the output port is changed to be high when the output power is at the first output power level and low when the output power is at the second output power level.

7. The method of claim 5 , wherein the impedance coupled to the output port of the power amplifier is changed based on a pulse width modulation signal.

8. A power amplifier circuit, comprising:

an attenuator configured to adjustably attenuate an envelope modulated radio frequency (RF) signal;

a power amplifier configured to amplify an output of the attenuator;

a variable load matching circuit connected to an output of the power amplifier, the variable load matching circuit configured to have a variable input impedance that is switchable between a first impedance state and a second impedance state so that an output power level of the power amplifier switches between a first power level and a second power level that is greater than the first power level; and

a filter configured to recover the envelope modulated RF signal responsive to an output of the variable load matching circuit.

9. The power amplifier circuit of claim 8 , further comprising:

a pulse width modulation (PWM) signal generator configured to generate a PWM signal responsive to the envelope modulated RF signal,

wherein the attenuator is configured to adjust attenuation and the variable load matching circuit is configured to switch the variable input impedance responsive to the PWM signal.

10. The power amplifier circuit of claim 8 , wherein the attenuator comprises a gain adjusting circuit including a shunt resistor and a switch configured to switch the shunt resistor.

11. The power amplifier circuit of claim 8 , wherein the attenuator comprises:

a power limiter configured to limit power of the envelope modulated RF signal so as not to be higher than a predetermined power level; and

a gain adjusting circuit connected to an output of the power limiter and including a shunt resistor and a switch configured to switch the shunt resistor.

12. The power amplifier circuit of claim 8 , wherein the variable load matching circuit is configured so that the input impedance is high when the output power level of the power amplifier is at the first power level and low when the output power level of the power amplifier is at the second power level.

13. The power amplifier circuit of claim 8 , wherein the variable load matching circuit comprises a shunt capacitor and a switch configured to switch the shunt capacitor.

14. A power amplifier circuit, comprising:

a power amplifier configured to amplify an envelope modulated radio frequency (RF) signal;

a variable load matching circuit coupled to an output port of the power amplifier, the variable load matching circuit configured to have an input impedance that is changeable so that an output power of the power amplifier changes between a first output power level and a second output power level which is higher than the first output power level;

an attenuator coupled to an input port of the power amplifier, the attenuator comprising: a power limiter configured to limit power of an input signal so as not to be higher than a predetermined power level; and a gain adjusting circuit connected to an output of the power limiter and including a shunt resistor and a switch configured to switch the shunt resistor, wherein attenuator is configured to change a gain of the power amplifier so that the power amplifier operates in a saturation region.

15. The power amplifier circuit of claim 14 , wherein the variable load matching circuit is configured so that the input impedance is high when the output power of the power amplifier is at the first output power level and low when the output power of the power amplifier is at the second output power level.

16. The power amplifier circuit of claim 14 , wherein the variable load matching circuit comprises a shunt capacitor and a switch configured to switch the shunt capacitor.

17. The power amplifier circuit of claim 14 , further comprising a pulse width modulation (PWM) signal generator configured to generate a PWM signal, wherein the input impedance of the variable load matching circuit is switched based on the PWM signal.

18. A power amplifier circuit, comprising:

a power amplifier configured to amplify an envelope modulated radio frequency (RF) signal;

a variable load matching circuit coupled to an output port of the power amplifier, the variable load matching circuit configured to have an input impedance that is changeable so that an output power of the power amplifier changes between a first output power level and a second output power level which is higher than the first output power level;

an attenuator coupled to an input port of the power amplifier, the attenuator configured to change a gain of the power amplifier so that the power amplifier operates in a saturation region; and

a pulse width modulation (PWM) signal generator configured to generate a PWM signal, wherein the attenuator switches the gain of the power amplifier based on the PWM signal.

19. The power amplifier circuit of claim 18 , wherein the variable load matching circuit is configured so that the input impedance is high when the output power of the power amplifier is at the first output power level and low when the output power of the power amplifier is at the second output power level.

20. The power amplifier circuit of claim 18 , wherein the variable load matching circuit comprises a shunt capacitor and a switch configured to switch the shunt capacitor.

21. The power amplifier circuit of claim 18 , wherein the attenuator comprises a gain adjusting circuit including a shunt resistor and a switch configured to switch the shunt resistor.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2013
From: JEON, MOON-SUK; WOO, JUNG-RIN; PARK, SUNG-HWAN; KIM, JUNG HYUN; KWON, YOUNG
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 031802/0713 →
Continuity (1)
Related Publication 20150091649A1 · Apr 2, 2015