Method of fabricating a flash memory comprising a high-K dielectric and a metal gate
View Patent ↗According to one exemplary embodiment, a method for fabricating a flash memory cell in a semiconductor die includes forming a control gate stack overlying a floating gate stack in a memory region of a substrate, where the floating gate stack includes a floating gate overlying a portion of a dielectric one layer. The floating gate includes a portion of a metal one layer and the dielectric o one layer includes a first high-k dielectric material. The control gate stack can include a control gate including a portion of a metal two layer, where the metal one layer can include a different metal than the metal two layer.
1. A method of fabricating a flash memory cell in a semiconductor die, said method comprising:
forming a control gate stack overlying a floating gate stack in a memory region of a substrate, said floating gate stack including a floating gate overlying a portion of a dielectric one layer, said floating gate comprising a portion of a metal one layer, and said dielectric one layer comprising a first high-k dielectric material, wherein
said control gate stack includes a control gate comprising a portion of a metal two layer, and
said control gate further comprises a portion of a polysilicon layer overlying said portion of said metal two layer.
2. The method of claim 1 , wherein said metal one layer comprises a different metal than said metal two layer.
3. The method of claim 1 , wherein said control gate stack further includes a dielectric two layer comprising a second high-k dielectric material.
4. The method of claim 1 , wherein said control gate stack further includes a dielectric two layer comprising said first high-k dielectric material.
5. The method of claim 1 , further comprising forming a gate stack in a first FET region of said substrate, wherein said gate stack includes a gate comprising a portion of said metal one layer.
6. The method of claim 5 , further comprising forming a gate stack in a second FET region of said substrate, wherein said gate stack in said second FET region of said substrate has an opposite conductivity type as said gate stack in said first FET region of said substrate.
7. The method of claim 1 , where said metal one layer comprises a metal selected from the group consisting of tantalum (Ta), tantalum nitride (TaN), and titanium nitride (TiN).
8. A method of fabricating a flash memory cell in a semiconductor die, said method comprising: forming a control gate stack overlying a floating gate stack, said floating gate stack including a floating gate overlying a portion of a dielectric layer, said floating gate comprising a portion of a metal layer, and said dielectric layer comprising a first high-k dielectric material, wherein
said control gate stack includes a control gate comprising a portion of another metal layer, and
said control gate further comprises a portion of a polysilicon layer overlying said portion of said another metal layer.
9. The method of claim 8 , wherein said control gate stack further includes another dielectric layer comprising a second high-k dielectric material.
10. The method of claim 8 , wherein said control gate stack further includes another dielectric layer comprising said first high-k dielectric material.
11. The method of claim 8 further comprising forming a gate stack in a first FET region, wherein said gate stack in said first FET region includes a gate comprising a portion of said metal layer.
12. The method of claim 11 further comprising forming a gate stack in a second FET region, wherein said gate stack in said second FET region of said substrate has an opposite conductivity type relative to said gate stack in said first FET region.
13. The method of claim 8 , wherein said metal layer comprises a metal selected from the group consisting of tantalum (Ta); tantalum nitride (TaN), and titanium nitride (TiN).
14. A method of fabricating a flash memory cell in a semiconductor die, said method comprising:
forming a control gate stack overlying a floating gate stack in a memory region of a substrate, said floating gate stack including a floating gate overlying a portion of a dielectric one layer, said floating gate comprising a portion of a metal one layer, and said dielectric one layer comprising a first high-k dielectric material, wherein
said floating gate further comprises a portion of a polysilicon layer overlying said portion of said metal one layer.
15. A method of fabricating a flash memory cell in a semiconductor die, said method comprising: forming a control gate stack overlying a floating gate stack, said floating gate stack including a floating gate overlying a portion of a dielectric layer, said floating gate comprising a portion of a metal layer, and said dielectric layer comprising a first high-k dielectric material, wherein
said floating gate further comprises a portion of a polysilicon layer overlying said portion of said metal layer.
16. The method of claim 1 , wherein said portion of said polysilicon layer is in direct contact with said portion of said metal two layer.
17. The method of claim 8 , wherein said portion of said polysilicon layer is in direct contact with said portion of said another metal layer.