Liquid crystal display device, driving method for liquid crystal display devices, and inspection method for liquid crystal display devices
View Patent ↗Using technology which uses a single shift register and simultaneously generates multiple pulses, this invention is a liquid crystal display device which rapidly drives data lines. It is possible to increase the frequency of the shift register output signal without changing the frequency of the shift register operation clock. If the shift register output signals, by means of analog switches, are used to determine the video signal sampling timing, high speed data line driving can be realized. Additionally, if the output signals of the shift register mentioned above are used to determine the video signal latch timing in a digital driver, high speed latching of the video signal can be realized. Consequently, even if the driving circuits of the liquid crystal display matrix are composed of TFTs, high speed operation of the driving circuits is possible without increasing power consumption. The shift register can also be used to inspect the electrical characteristics of the data lines and analog switches.
1. A driving circuit, comprising:
a plurality of switches including N switch groups, one of the N switch groups including M switches, the N being a natural number that is more than 1, the M being a natural number that is more than 1;
N video signal lines, one of the N video signal lines transmitting multiplexed video signals, the one of the N video signal lines being electrically connected to the M switches of one of the N switch groups;
timing signals lines transmitting timing signals to the plurality of switches;
one of the M switches being driven by one of the timing signals to output video signal contained in the multiplexed video signals;
N of the plurality of switches, each of which being included in a different switch groups, being simultaneously driven; and
a first switch, a second switch and a third switch of the plurality of switches, the first switch and the second switch being driven at a first timing, the third switch being driven at a second timing different from the first timing, the third switch being disposed between the first switch and the second switch.
2. A driving circuit, comprising:
a plurality of switches including N switch groups, one of the N switch groups including M switches, the N being a natural number that is more than 1, the M being a natural number that is more than 1;
N video signal lines, one of the N video signal lines transmitting multiplexed video signals, the one of the N video signal lines being electrically connected to the M switches of one of the N switch groups;
timing signals lines transmitting timing signals to the plurality of switches;
one of the M switches being driven by one of the timing signals to output video signal contained in the multiplexed video signals; and
a first switch and a second switch of the plurality of switches being driven at a first timing, the first switch and the second switch being included in a different switch groups, a third switch of the plurality of switches being disposed between the first switch and the second switch, the third switch being driven at a second timing different from the first timing.
3. A driving circuit, comprising:
a plurality of switches including N switch groups, one of the N switch groups including M switches, the N being a natural number that is more than 1, the M being a natural number that is more than 1;
N video signal lines, one of the N video signal lines being electrically connected to the M switches of one of the N switch groups, the one of the N video signal lines transmitting multiplexed video signals, the multiplexed video signals including a video signal, one of the M switches being driven by a timing signal to output the video signal; and
a first switch and a second switch positioned in one of the N switch groups and a third switch positioned in another of the N switch groups, the second switch being disposed between the first switch and the third switch, the first switch and the third switch being driven at a first timing, the second switch being driven at a second timing different from the first timing.