IP Library Granted Patent US 9,130,678
Granted Patent B2
US 9,130,678 · App. 14/102,856 · Granted Sep 8, 2015

High speed signal generator

Inventors: David Krause (Nepean, CA); Charles Laperle (Kanata, CA); Kim B. Roberts (Nepean, CA)
Assignee: CIENA CORPORATION
H04B10/516H04B10/5055H04L27/2627
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,130,678
App. No.
14/102,856
Granted
Sep 8, 2015
Kind
B2
Abstract

A high-speed signal generator. A digital signal processing (DSP) block generates a set of N (where N is an integer and N≧2) parallel digital sub-band signals, each digital sub-band signal having frequency components within a spectral range between 0 Hz and ±Fs/2, where Fs is a sample rate of the digital sub-band signals. A respective Digital-to-Analog Converter (DAC) processes each digital sub-band signal to generate a corresponding analog sub-band signal, each DAC having a sample rate of Fs/2. A combiner combines the analog sub-band signals to generate an output analog signal having frequency components within a spectral range between 0 Hz and ±NFs/2.

Claims (34)

1. A high-speed signal generator comprising:

a digital signal processing (DSP) block configured to generate a set of N (where N is an integer and N≧2) parallel digital sub-band signals, each digital sub-band signal having frequency components within a spectral range between 0 Hz and ±Fs/2, where Fs is a sample rate of the digital sub-band signals;

a respective Digital-to-Analog Converter (DAC) configured to process each digital sub-band signal to generate a corresponding analog sub-band signal, each DAC having a sample rate of Fs/2; and

a combiner configured to combine the analog sub-band signals to generate an output analog signal having frequency components within a spectral range between 0 Hz and ±N·Fs/2, wherein the combiner is configured to combine the analog sub-band signals in the optical domain;

wherein the digital signal processing (DSP) block comprises:

an encoding block configured to process an input digital signal to generate an encoded digital signal representative of the output analog signal;

a Fast Fourier Transform (FFT) block configured to compute an array representative of a spectrum of the encoded digital signal;

a Frequency Domain Processor (FDP) configured to process the array to generate a set of N sub-band arrays, each sub-band array including spectral components for a respective one of the parallel digital sub-band signals; and

a respective Inverse Fast Fourier Transform (IFFT) block configured to process each sub-band array to generate a corresponding digital sub-band signal.

2. In an optical communications system, a transmitter comprising:

a digital signal processing (DSP) block configured to generate a set of N (where N is an integer and N≧2) parallel digital sub-band signals, each digital sub-band signal having frequency components within a spectral range between 0 Hz and ±Fs/2, where Fs is a sample rate of the digital sub-band signals;

a respective Digital-to-Analog Converter (DAC) configured to process each digital sub-band signal to generate a corresponding analog sub-band signal, each DAC having a sample rate of Fs/2; and

a combiner configured to combine the analog sub-band signals to generate an output analog signal having frequency components within a spectral range between 0 Hz and ±N·Fs/2, wherein the combiner is configured to combine the analog sub-band signals in the optical domain;

wherein the digital signal processing (DSP) block comprises:

an encoding block configured to process an input digital signal to generate an encoded digital signal representative of the output analog signal;

a Fast Fourier Transform (FFT) block configured to compute an array representative of a spectrum of the encoded digital signal;

a Frequency Domain Processor (FDP) configured to process the array to generate a set of N sub-band arrays, each sub-band array including spectral components for a respective one of the parallel digital sub-band signals; and

a respective Inverse Fast Fourier Transform (IFFT) block configured to process each sub-band array to generate a corresponding digital sub-band signal.

3. The signal generator as claimed in claim 1 , further comprising a mixer configured to heterodyne a respective one of the analog sub-band signals with a Local Oscillator (LO) signal having a selected LO frequency, for up-converting the respective analog sub-band signal to an RF band.

4. The signal generator as claimed in claim 3 , wherein the mixer is an image rejection mixer.

5. The signal generator as claimed in claim 3 , wherein the LO frequency is an integer multiple of Fs/2.

6. The signal generator as claimed in claim 3 , wherein the mixer is a double side-band mixer.

7. The signal generator as claimed in claim 1 , further comprising at least one delay element configured to impose a predetermined phase offset between a pair of analog sub-band signals.

8. The signal generator as claimed in claim 7 , wherein the predetermined phase offset is fixed.

9. The signal generator as claimed in claim 7 , wherein the predetermined phase offset is adjustable.

10. The signal generator as claimed in claim 7 , wherein the predetermined phase offset is not zero.

11. The transmitter as claimed in claim 2 , further comprising a mixer configured to heterodyne a respective one of the analog sub-band signals with a Local Oscillator (LO) signal having a selected LO frequency, for up-converting the respective analog sub-band signal to an RF band.

12. The transmitter as claimed in claim 11 , wherein the mixer is an image rejection mixer.

13. The transmitter as claimed in claim 11 , wherein the LO frequency is an integer multiple of Fs/2.

14. The transmitter as claimed in claim 11 , wherein the mixer is a double side-band mixer.

15. The transmitter as claimed in claim 2 , further comprising at least one delay element configured to impose a predetermined phase offset between a pair of analog sub-band signals.

16. The transmitter as claimed in claim 15 , wherein the predetermined phase offset is fixed.

17. The transmitter as claimed in claim 15 , wherein the predetermined phase offset is adjustable.

18. The transmitter as claimed in claim 15 , wherein the predetermined phase offset is not zero.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2023
From: BANK OF AMERICA, N.A.
To: CIENA CORPORATION
Reel/Frame 065630/0232 →
PATENT SECURITY AGREEMENT Recorded Nov 8, 2019
From: CIENA CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 050969/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 30, 2019
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: CIENA CORPORATION
Reel/Frame 050938/0389 →
PATENT SECURITY AGREEMENT Recorded Jul 16, 2014
From: CIENA CORPORATION
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 033347/0260 →
SECURITY INTEREST Recorded Jul 15, 2014
From: CIENA CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 033329/0417 →
Continuity (3)
Division 12692065 · Jan 22, 2010
Provisional Application 61146901 · Jan 23, 2009
Related Publication 20140161469A1 · Jun 12, 2014