Semiconductor package with bonding wires of reduced loop inductance
A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers, a plurality of first power supply voltage bond fingers, and a plurality of second power supply voltage bond fingers. The signal pads are connected respectively to the signal bond fingers by first wires. The first power supply voltage bond fingers and the second power supply voltage bond fingers are connected respectively to the auxiliary pads by second wires. The first wires are disposed between those of the second wires which are connected to the first power supply voltage bond fingers and those of the second wires which are connected to the second power supply voltage bond fingers.
1. A semiconductor device comprising:
a board having a plurality of bond fingers, said plurality of bond fingers including power bond fingers, ground bond fingers and signal bond fingers;
a plurality of semiconductor chips, including first and second semiconductor chips, the plurality of semiconductor chips being stacked and mounted on the board, each of the plurality of semiconductor chips having an inner row of pads and an outer row of pads along one edge thereof,
the outer row comprising a plurality of power pads and ground pads,
the inner row comprising a plurality of power pads, ground pads and signal pads,
the plurality of power pads in the inner row and the plurality of power pads in the outer row being interconnected, and
the plurality of ground pads in the inner row and the plurality of ground pads in the outer row being interconnected;
a first plurality of wires connecting power pads within the inner row of the first semiconductor chip, mounted on the board, to power pads within the outer row of the second semiconductor chip, mounted on top of the first semiconductor chip;
a second plurality of wires connecting ground pads within the inner row of the first semiconductor chip to ground pads within the outer row of the second semiconductor chip;
a third plurality of wires connecting signal pads within the inner row of the first semiconductor chip to signal pads within the inner row of the second semiconductor chip;
a fourth plurality of wires connecting power pads within the outer rows of the first semiconductor chip to power bond fingers on the board;
a fifth plurality of wires connecting ground pads within the outer row of the first semiconductor chip to the ground bond fingers on the board; and
a sixth plurality of wires connecting signal pads within the inner row of the first or second semiconductor chip to the signal bond fingers on the board, wherein individual wires of the sixth plurality of wires are disposed between respective individual wires of the fourth plurality of wires and the fifth pluralities of wires.
2. The semiconductor device of claim 1 , wherein the plurality of power pads in the inner row, the plurality of power pads in the outer row, the plurality of ground pads in the inner row and the plurality of ground pads in the outer row are interconnected through a redistribution layer.
3. The semiconductor device of claim 1 , wherein the outer row comprises alternating power pads and ground pads.
4. The semiconductor device of claim 1 , wherein the plurality of bond fingers on the board are arranged in two rows, said two rows including a first row, closest to the first semiconductor chip, having power and ground bond fingers, and a second row having signal bond fingers.
5. The semiconductor device of claim 1 , wherein the board comprises a package board having a plurality of bond fingers.
6. The semiconductor device of claim 5 , wherein the plurality of bond fingers of the package board includes power bond fingers, ground bond fingers and signal bond fingers.