PFC signal generation circuit, PFC control system using the same, and PFC control method
A PFC signal generation circuit which generates a PFC signal to control a PFC circuit including a first inductor connected to a first switch and a second inductor connected to a second switch includes: a counter whose count value is cleared based on a first timing when a zero current of the first inductor is detected; a counter clear control circuit that clears the counter value after waiting until a cycle lower limit is reached, when the first timing is below the cycle lower limit; a first control signal output unit that outputs a first PFC signal to turn on the first switch at a timing when the count value is cleared; and a second control signal output unit that outputs a second PFC signal to turn on the second switch based on a second timing when a zero current of the second inductor is detected.
1. A Power Factor Correction (PFC) signal generation circuit that generates a PFC signal to control a PFC circuit including a first inductor connected to a first switch and a second inductor connected to a second switch, the PFC signal generation circuit comprising:
a counter whose count value is cleared at a first timing at which a zero current of the first inductor is detected, when the first timing is equal to or above a cycle lower limit;
a counter clear control circuit that clears the count value after waiting until the cycle lower limit is reached, when the first timing is below the cycle lower limit;
a first control signal output unit that outputs a first PFC signal to turn on the first switch at a timing when the count value is cleared; and
a second control signal output unit that outputs a second PFC signal to turn on the second switch, based on a second timing at which a zero current of the second inductor is detected.
2. The PFC signal generation circuit according to claim 1 , further comprising a first digital comparator that compares the count value of the counter with a set value of the cycle lower limit,
wherein the counter clear control circuit determines whether the first timing is below the cycle lower limit, based on a comparison result of the first digital comparator.
3. The PFC signal generation circuit according to claim 1 , further comprising a second digital comparator that compares the count value of the counter with a set value of a pulse width of the first PFC signal determined based on a feedback signal from the PFC circuit.
4. The PFC signal generation circuit according to claim 1 , further comprising a down-counter that counts down a set value of a pulse width of the second PFC signal determined based on a feedback signal from the PFC circuit.
5. The PFC signal generation circuit according to claim 4 , further comprising a second digital comparator that compares the count value of the counter with a set value of a pulse width of the first PFC signal determined based on the feedback signal.
6. A Power Factor Correction (PFC) control system comprising:
a PFC circuit connected to an AC power supply; and
a PFC signal generation circuit that generates a PFC signal to control the PFC circuit, wherein
the PFC circuit comprises:
a first inductor connected to a first switch; and
a second inductor connected to a second switch, and
the PFC signal generation circuit comprises:
a counter whose count value is cleared at a first timing at which a zero current of the first inductor is detected, when the first timing is equal to or above a cycle lower limit;
a counter clear control circuit that clears the count value after waiting until the cycle lower limit is reached, when the first timing is below the cycle lower limit;
a first control signal output unit that outputs a first PFC signal to turn on the first switch at a timing when the count value is cleared; and
a second control signal output unit that outputs a second PFC signal to turn on the second switch, based on a second timing at which a zero current of the second inductor is detected.
7. A Power Factor Correction (PFC) control method that controls a PFC circuit including a first inductor connected to a first switch and a second inductor connected to a second switch, the PFC control method comprising:
clearing a count value of a counter at a first timing at which a zero current of the first inductor is detected, when the first timing is equal to or above a cycle lower limit;
turning on the first switch at a timing when the count value is cleared; and
turning on the second switch based on a second timing at which a zero current of the second inductor is detected,
wherein in the clearing of the count value of the counter, when the first timing is below the cycle lower limit, the count value is cleared after waiting until the cycle lower limit is reached.
8. The PFC signal generation circuit according to claim 1 , wherein the counter clear control circuit determines whether the first timing is below the cycle lower limit based on a count value of the counter.
9. The PFC control system according to claim 6 , wherein the counter clear control circuit determines whether the first timing is below the cycle lower limit based on a count value of the counter.
10. The PFC control method according to claim 7 , wherein the first timing is determined to be below the cycle lower limit based on a count value of the counter.
11. A Power Factor Correction (PFC) signal generation circuit that generates a PFC signal to control a PFC circuit including a first inductor connected to a first switch, the PFC signal generation circuit comprising:
a counter whose count value is cleared at a first timing at which a zero current of the first inductor is detected, when the first timing is equal to or above a cycle lower limit;
a counter clear control circuit that clears the count value after waiting until the cycle lower limit is reached, when the first timing is below the cycle lower limit; and
a first control signal output unit that outputs a first PFC signal to turn on the first switch at a timing when the count value is cleared.
12. The PFC signal generation circuit according to claim 11 , wherein the counter clear control circuit determines whether the first timing is below the cycle lower limit based on a count value of the counter.