Semiconductor device outputting read data in synchronization with clock signal
View Patent ↗A method for outputting data in a semiconductor device includes receiving an external clock signal, synchronizing, in a delay locked loop of the semiconductor device, a first internal clock signal to the external clock signal during a read period, synchronizing, in the delay locked loop, a second internal clock signal to the external clock signal during an active period, the second internal clock signal having a period longer than the first internal clock signal, and outputting data synchronized with the first internal clock signal during the read period.
1. A method for outputting data in a semiconductor device comprising:
receiving an external clock signal;
synchronizing, in a delay locked loop of the semiconductor device, a first internal clock signal to the external clock signal during a read period;
synchronizing, in the delay locked loop, a second internal clock signal to the external clock signal during an active period, the second internal clock signal having a period longer than the first internal clock signal; and
outputting data synchronized with the first internal clock signal during the read period.
2. The method as claimed in claim 1 , further comprising disabling the delay locked loop in a clock-stop mode.
3. The method as claimed in claim 1 , wherein the period of the first clock signal is the same as the period of the external clock signal.
4. The method as claimed in claim 1 , wherein the second clock signal is generated by dividing an output of the delay locked loop.
5. The method as claimed in claim 1 , wherein the second clock signal has a period n times the period of the first clock signal, where n is an integer.
6. The method as claimed in claim 5 , wherein the second clock signal has twice the period of the first clock signal.
7. The method as claimed in claim 5 , wherein the second clock signal has four times the period of the first clock signal.
8. The method as claimed in claim 1 , further comprising outputting the first clock signal.
9. The method as claimed in claim 1 , wherein the output data is synchronized with both edges of the first clock signal.
10. The method as claimed in claim 1 , further comprising adjusting the duty ratio of the first clock signal.
11. The method as claimed in claim 10 , wherein the duty ratio of the first clock signal is adjusted to approximately 50/50.
12. The method as claimed in claim 1 , wherein the output data is read from a memory array.
13. The method as claimed in claim 12 , wherein the output data is read from a dynamic memory array.
14. The method as claimed in claim 1 , wherein the semiconductor device is a synchronous dynamic random access memory.
15. The method as claimed in claim 14 , wherein the semiconductor device is a double data rate synchronous dynamic random access memory.