Semiconductor device including guard ring and groove
A semiconductor device includes a semiconductor substrate having a peripheral edge, a first surface, and a second surface opposite to the first surface, an inter-layer insulator including a guard ring formed on the first surface, adjacent to the peripheral edge of the semiconductor substrate, a first groove formed on the second surface, adjacent to the peripheral edge of the semiconductor substrate, and a through electrode penetrating the second surface to the inter-layer insulator near the groove and on an opposite side of the groove with respect to the peripheral edge.
1. A semiconductor device comprising:
a semiconductor substrate having a peripheral edge, a first surface, and a second surface opposite to the first surface;
an inter-layer insulator including a guard ring formed on the first surface, adjacent to the peripheral edge of the semiconductor substrate;
a first groove formed on the second surface, adjacent to the peripheral edge of the semiconductor substrate; and
a through electrode penetrating the second surface to the inter-layer insulator near the groove and on an opposite side of the groove with respect to the peripheral edge.
2. The semiconductor device according to claim 1 , wherein the first groove extends around all peripheral edges of the semiconductor substrate.
3. The semiconductor device according to claim 1 , wherein the first groove at least partially overlaps the guard ring.
4. The semiconductor device according to claim 1 , wherein the first groove comprises an interrupted groove.
5. The semiconductor device according to claim 1 , further comprising:
an additional groove formed adjacent to the first groove.
6. The semiconductor device according to claim 1 , wherein the through electrode comprises a support through electrode.
7. The semiconductor device according to claim 1 , further comprising:
a plurality of operational through electrodes in a central region of the semiconductor substrate.
8. The semiconductor device according to claim 1 , further comprising:
a memory device.
9. The semiconductor device according to claim 1 , further comprising:
a dynamic random access memory (DRAM).
10. A wafer comprising a semiconductor device according to claim 1 .