IP Library Granted Patent US 9,299,303
Granted Patent B2
US 9,299,303 · App. 14/140,241 · Granted Mar 29, 2016

Liquid crystal display device

Inventors: Osamu Nagashima (Mobara, JP); Takahiro Nagami (Mobara, JP)
Assignees: Japan Display Inc.; Panasonic Liquid Crystal Display Co., LTD
G09G3/3655G02F1/1362H01L27/124H01L27/1214G02F1/136286G09G3/3607G09G2300/0426H01L27/3248H01L27/3262H01L27/3265
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,299,303
App. No.
14/140,241
Granted
Mar 29, 2016
Kind
B2
Abstract

A display device includes a first gate signal line and a second gate signal line, and a first drain signal line, a second drain signal line, and a third drain signal line. A first pixel and a second pixel are surrounded by the first gate signal line, the second gate signal line, the first drain signal line, and the second drain signal line, and a third pixel and a fourth pixel are surrounded by the first gate signal line, the second gate signal line, the second drain signal line, and the third drain signal line. A first storage line and a second storage line are disposed between the first gate signal line and the second gate signal line, and the first pixel includes a first thin film transistor connected to the first gate signal line, the first drain signal line, and a first pixel electrode of the first pixel.

Claims (42)

1. A display device comprising:

a first gate signal line and a second gate signal line;

a first drain signal line, a second drain signal line, and a third drain signal line;

a first pixel and a second pixel surrounded by the first gate signal line, the second gate signal line, the first drain signal line, and the second drain signal line, and a third pixel and a fourth pixel surrounded by the first gate signal line, the second gate signal line, the second drain signal line, and the third drain signal line; and

a first storage line and a second storage line disposed between the first gate signal line and the second gate signal line,

wherein the first pixel comprises a first thin film transistor connected to the first gate signal line, the first drain signal line, and a first pixel electrode of the first pixel,

wherein the second pixel comprises a second thin film transistor connected to the second gate signal line, the second drain signal line, and a second pixel electrode of the second pixel,

wherein the third pixel comprises a third thin film transistor connected to the second drain signal line and a third pixel electrode of the third pixel,

wherein the first storage line is disposed adjacent to the first thin film transistor and the second storage line is disposed adjacent to the second thin film transistor, and

wherein a third storage line is disposed between the first pixel electrode and the second pixel electrode, and connected to the first storage line and the second storage line.

2. A display device according to claim 1 , wherein the first storage line has a region with a wide width in a portion thereof close to the first thin film transistor, and the second storage line has a range with a wide width in a portion thereof close to the second thin film transistor.

3. A liquid crystal display device according to claim 1 , wherein an organic insulating film covers each of the thin film transistors, and each of the pixel electrodes are formed on the upper surface of the organic insulating film.

4. A display device according to claim 1 , wherein the first pixel electrode and the second pixel electrode are overlapped with the third storage line.

5. A liquid crystal display device according to claim 4 , wherein an organic insulating film covers each of the thin film transistors, and each of the pixel electrodes are formed on the upper surface of the organic insulating film.

6. A liquid crystal display device according to claim 1 ,

wherein the fourth pixel comprises a fourth thin film transistor connected to the third drain signal line and a fourth pixel electrode of the fourth pixel, and

wherein a fourth storage line is disposed between the third pixel electrode and the fourth pixel electrode, and electrically connected to the first storage line and the second storage line.

7. A display device according to claim 6 , wherein the first storage line has a region with a wide width in a portion thereof close to the first thin film transistor, and the second storage line has a region with a wide width in a portion thereof close to the second thin film transistor.

8. A liquid crystal display device according to claim 6 , wherein an organic insulating film covers each of the thin film transistors, and each of the pixel electrodes are formed on the upper surface of the organic insulating film.

9. A display device according to claim 6 , wherein the third pixel electrode and the fourth pixel electrode are overlapped with the fourth storage line.

10. A liquid crystal display device according to claim 9 , wherein an organic insulating film covers each of the thin film transistors, and each of the pixel electrodes are formed on the upper surface of the organic insulating film.

11. A display device comprising:

a first gate signal line and a second gate signal line;

a first drain signal line, a second drain signal line, and a third drain signal line;

a first pixel and a second pixel surrounded by the first gate signal line, and second gate signal line, the first drain signal line, and the second drain signal line, and a third pixel and a fourth pixel surrounded by the first gate signal line, the second gate signal line, the second drain signal line, and the third drain signal line; and

a first storage line and a second storage line disposed between the first gate signal line and the second gate signal line;

wherein the first pixel comprises a first thin film transistor connected to the first gate signal line, the first drain signal line, and a first pixel electrode of the first pixel;

wherein the second pixel comprises a second thin film transistor connected to the second gate signal line, the second drain signal line, and a second pixel electrode of the second pixel;

wherein the third pixel comprises a third thin film transistor connected to the second drain signal line and a third pixel electrode of the third pixel;

wherein the first storage line is overlapped with the first pixel electrode, and the second storage line is overlapped with the second thin pixel electrode; and

wherein a third storage line is disposed between the first pixel electrode and the second pixel electrode, and connected to the first storage line and the second storage line.

12. A display device according to claim 11 , wherein the first pixel electrode and the second pixel electrode are overlapped with the third storage line.

13. A liquid crystal display device according to claim 12 , wherein an organic insulating film covers each of the thin film transistors, and each of the pixel electrodes are formed over the upper surface of the organic insulating film.

14. A display device according to claim 11 , wherein the first storage line has a region with a wide width in a portion thereof close to the first thin film transistor, and the second storage line has a region with a wide width in a portion thereof close to the second thin film transistor.

15. A liquid crystal display device according to claim 14 , wherein an organic insulating film covers each of the thin film transistors, and each of the pixel electrodes are formed over the upper surface of the organic insulating film.

16. A liquid crystal display device according to claim 11 ,

wherein the fourth pixel comprises a fourth thin film transistor connected to the third drain signal line and a fourth pixel electrode of the fourth pixel, and

wherein a fourth storage line is disposed between the third pixel electrode and the fourth pixel electrode, electrically connected to the third line.

17. A display device according to claim 16 , wherein the third pixel electrode and the fourth pixel electrode are overlapped with the fourth storage line.

18. A liquid crystal display device according to claim 17 , wherein an organic insulating film covers each of the thin film transistors, and each of the pixel electrodes are formed over the upper surface of the organic insulating film.

19. A display device according to claim 16 , wherein the first storage line has a region with a wide width in a portion thereof close to the first thin film transistor, and the second storage line has a region with a wide width in a portion thereof close to the second thin film transistor.

20. A liquid crystal display device according to claim 19 , wherein an organic insulating film covers each of the thin film transistors, and each of the pixel electrodes are formed on the upper surface of the organic insulating film.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2025
From: JAPAN DISPLAY INC
To: MAGNOLIA PURPLE CORPORATION
Reel/Frame 071890/0202 →
NUNC PRO TUNC ASSIGNMENT Recorded Nov 17, 2023
From: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
To: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Reel/Frame 065615/0327 →
Priority Claims (2)
JP 2009-161355 · Jul 8, 2009 · national
JP 2009-227362 · Sep 30, 2009 · national
Continuity (2)
Continuation 12773098 · May 4, 2010
Related Publication 20140104150A1 · Apr 17, 2014