Constrained on-the-fly interleaver address generator circuits, systems, and methods

1. A non-transitory computer-readable storage medium containing software instructions which, when executed by a computer, cause the computer to perform the method comprising:

interleaving a block of data containing a plurality of subwords, the interleaving including the operations of,

for each subword having and N columns and M rows defining an array space,

generating a land address corresponding to one of the N columns;

providing for each of the N columns a seed value to a linear feedback shift register;

clocking the linear feedback shift register to generate pseudo random circulant addresses;

providing a seed value to a linear feedback shift register to generate subcirculant addresses; and

permuting bits of a data block in a first domain to different location in a data block in a second domain using the selected columns, circulant, and sub-circulant addresses.

2. The non-transitory computer-readable storage medium of claim 1 ,

wherein providing for each of the N columns a seed value to a linear feedback shift er comprises providing the seed value to the linear feedback shift register having a degree of 5; and

wherein providing a seed value to a linear feedback shift register to generate subcirculant addresses comprises providing the seed value to the linear feedback shift register having a degree of 6.

3. The non-transitory computer-readable storage medium of claim 1 further comprising software instructions which, when executed by a computer, cause the computer to perform the operation of deinterleaving the bits in the block of data in the second domain to the first domain.

4. The non-transitory computer-readable storage medium of claim 3 , wherein the computer comprises one of a personal computer and a smart phone.

5. The non-transitory computer-readable storage medium of claim 4 further comprising instructions for instructing a computer to perform the operation of deinterleaving the bits in the block of data in the second domain to the first domain.

6. A non-transitory computer-readable storage medium containing software instructions which, when executed b a computer, cause the computer to perform the method comprising:

interleaving a block of data containing a plurality of subwords, the interleaving including the operations of,

for each subword having and N columns and M rows defining an array space,

generating a land address corresponding to one of the N columns;

providing for each of the N columns a seed value to a linear feedback shift resister of degree 5;

clocking the linear feedback shift register to generate pseudo random circulant addresses;

providing a seed value to a linear feedback shift register of degree 6 to generate subcirculant addresses; and

permuting bits of a data block in a first domain to different location in a data block in a second domain using the selected columns, circulant, and sub-circulant addresses.

7. A method, comprising:

generating addresses for permuting a data block in a first domain to a data block in a second domain on a subword basis using a plurality of linear feedback shift registers;

generating lane addresses for each subword; and

generating circulant addresses and sub-circulant addresses to map bits in each subword in the data block in the first domain to a corresponding subword in the second domain using the linear feedback registers.

8. The method of claim 7 , wherein each subword includes an array space including N columns and M rows, and wherein the method further comprises selecting one of the N columns of the array space for which mapping addresses are generated.

9. The method of claim 7 ,

wherein there are N linear feedback shift registers, and

wherein the method further comprises generating circulant addresses for a corresponding column in the array space of a given subword using a respective one of the N linear feedback shift registers for each column.

10. The method of claim 9 further comprising providing an independent seed value to each of the N linear feedback shift registers.

11. The method of claim 10 ,

wherein there are P linear feedback shift registers where P is the number of subwords contained in each data block, and

wherein the method further comprises generating sub-circulant addresses for a corresponding subword using a respective one of the P linear feedback shift registers.

12. A method, comprising:

receiving input message bits and operable to encode these input message bits and store this encoded data on a storage medium;

generating addresses using a plurality of linear feedback shift registers, the addresses being used to interleave user and parity data in a decoder domain to interleaved codewords in an ISI domain;

writing the interleaved codewords onto a storage medium;

reading encoded data stored on the storage medium;

decoding this encoded data to output the input message bits originally supplied;

generating addresses using a plurality of linear feedback shift registers, the addresses being used to deinterleave encoded data stored on the storage medium in the ISI domain to deinterleaved codewords in an ISI domain.

13. The method of claim 12 , wherein writing the interleaved codewords onto a storage medium comprises cyclic redundancy check (CRC) and run length limited (RLL) encoding.

14. The method of claim 13 , wherein reading encoded data stored on the storage medium comprises CRC and RLL decoding.

15. The method of claim 13 , wherein the storage medium comprises a magnetic storage media.