Power amplifier
A linearized power amplifier includes a first amplification stage having a first transistor for amplifying an input signal and outputting a pre-amplified signal, and a second amplification stage having a second transistor for amplifying the pre-amplified signal. A phase injection circuit, connected to the gate of the first transistor and the gate of the second transistor, adjusts the phase of the input signal based on the pre-amplified signal so as to compensate for AM-AM distortion and AM-PM distortion.
1. A power amplifier, comprising:
a first amplification stage including a first transistor configured to amplify an input signal and output a pre-amplified signal;
a second amplification stage including a second transistor configured to amplify the pre-amplified signal; and
a phase injection circuit, connected to a gate of the first transistor and a gate of the second transistor, configured to adjust a phase of the input signal based on the pre-amplified signal, the phase injection circuit comprising: an envelope detection unit configured to generate an envelope signal from the pre-amplified signal; and a phase control unit configured to adjust the phase of the input signal based on a magnitude of the envelope signal.
2. The power amplifier of claim 1 , wherein the phase control unit comprises a varactor having a cathode connected to ground via a first shunt capacitor, and an anode connected to the gate of the first transistor via a second shunt capacitor, and
wherein the phase control unit is configured to adjust a capacitance of the varactor to a predetermined value if the magnitude of the envelope signal is equal to or smaller than a predetermined level, and to adjust the capacitance of the varactor to a value that is smaller than the predetermined value if the magnitude of the envelope signal is greater than the predetermined level.
3. The power amplifier of claim 2 , wherein the phase control unit further comprises a first field-effect transistor (FET) and a second FET, a gate and a drain of the first FET being respectively connected to a gate and a drain of the second FET, and
wherein the drain of the first FET and the drain of the second FET are connected to the cathode of the varactor.
4. The power amplifier of claim 3 , wherein the envelope detection unit comprises a common-source FET having a gate connected to the gate of the second transistor, and having a drain connected to the gate of the first FET and the gate of the second FET.
5. The power amplifier of claim 1 , further comprising a hybrid bias circuit, connected to the gate of the first transistor, configured to adjust a bias voltage at the gate of the first transistor based on a magnitude of the input signal.
6. The power amplifier of claim 5 , wherein the hybrid bias circuit comprises:
a bias resistor connected to a first direct current (DC) voltage source supplying a first voltage and to the gate of the first transistor; and
a diode-connected FET having a source connected to the gate of the first transistor, a drain connected to a second DC voltage source supplying a second voltage which is lower than the first voltage, and a gate connected to the drain of the diode-connected FET.
7. The power amplifier of claim 6 , wherein when the magnitude of the input signal is equal to or smaller than a preset level, the bias voltage at the gate of the first transistor becomes substantially equal to the first voltage, and
when the magnitude of the input signal increases above the preset level, the bias voltage at the gate of the first transistor decreases to a voltage lower than the first voltage.
8. The power amplifier of claim 1 , further comprising an amplitude injection circuit connected to the gate of the second transistor,
wherein the amplitude injection circuit is configured to produce an envelope signal from the pre-amplified signal, and to adjust an amplitude of the envelope signal based on a magnitude of the pre-amplified signal, to thereby generate and output a reshaped envelope signal to the gate of the second transistor.
9. The power amplifier of claim 8 , wherein the amplitude injection circuit is configured to adjust an amplitude of the reshaped envelope signal to a predetermined level if the magnitude of the pre-amplified signal is equal to or smaller than a preset level, and to adjust the amplitude of the reshaped envelope signal to a level higher than the predetermined level if the magnitude of the pre-amplified signal is greater than the preset level.
10. The power amplifier of claim 1 , wherein the first transistor is a common-source transistor.
11. The power amplifier of claim 1 , wherein the second transistor is a common-source transistor.
12. A power amplifier, comprising:
a first amplification stage including a first transistor configured to amplify an input signal and output a pre-amplified signal;
a second amplification stage including a second transistor configured to amplify the pre-amplified signal;
a hybrid bias circuit, connected to a gate of the second transistor, configured to adjust a bias voltage at the gate of the second transistor based on a magnitude of the pre-amplified signal; and
a phase injection circuit, connected to a gate of the first transistor and the gate of the second transistor, configured to adjust a phase of the input signal based on the pre-amplified signal, the phase detection circuit comprising: an envelope detection unit configured to generate an envelope signal from the pre-amplified signal; and a phase control unit configured to adjust the phase of the input signal based on a magnitude of the envelope signal.
13. The power amplifier of claim 12 wherein the phase control unit comprises a varactor having a cathode connected to ground via a first shunt capacitor, and an anode connected to the gate of the first transistor via a second shunt capacitor, and
wherein the phase control unit is configured to adjust a capacitance of the varactor to a predetermined value if the magnitude of the envelope signal is equal to or smaller than a predetermined level, and to adjust the capacitance of the varactor to a value that is smaller than the predetermined value if the magnitude of the envelope signal is greater than the predetermined level.
14. The power amplifier of claim 13 , wherein the phase control unit further comprises a first FET and a second FET, a gate and a drain of the first FET being respectively connected to a gate and a drain of the second FET, and
wherein the drain of the first FET and the drain of the second FET are connected to the cathode of the varactor.
15. The power amplifier of claim 14 , wherein the envelope detection unit comprises a common-source FET having a gate connected to the gate of the second transistor, and having a drain connected to the gate of the first FET and the gate of the second FET.
16. The power amplifier of claim 12 , wherein the hybrid bias circuit comprises:
a bias resistor connected to a first DC voltage source supplying a first voltage and to the gate of the second transistor; and
a diode-connected FET having a source connected to the gate of the second transistor, a drain connected to a second DC voltage source supplying a second voltage which is lower than the first voltage, and a gate connected to the drain of the diode-connected FET.
17. The power amplifier of claim 16 , wherein when the magnitude of the pre-amplified signal is equal to or smaller than a preset level, the bias voltage at the gate of the second transistor becomes substantially equal to the first voltage, and
when the magnitude of the pre-amplified signal increases above the preset level, the bias voltage at the gate of the second transistor decreases to a voltage lower than the first voltage.
18. A power amplifier, comprising:
a first amplification stage including a first transistor configured to amplify an input signal and output a pre-amplified signal;
a second amplification stage including a second transistor configured to amplify the pre-amplified signal;
a phase injection circuit, connected to a gate of the first transistor and a gate of the second transistor, configured to adjust a phase of the input signal based on the pre-amplified signal; and
a hybrid bias circuit, connected to the gate of the first transistor, configured to adjust a bias voltage at the gate of the first transistor based on a magnitude of the input signal, the hybrid bias circuit comprising: a bias resistor connected to a first direct current (DC) voltage source supplying a first voltage and to the gate of the first transistor; and a diode-connected FET having a source connected to the gate of the first transistor, a drain connected to a second DC voltage source supplying a second voltage which is lower than the first voltage, and a gate connected to the drain of the diode-connected FET.
19. The power amplifier of claim 18 , wherein when the magnitude of the input signal is equal to or smaller than a preset level, the bias voltage at the gate of the first transistor becomes substantially equal to the first voltage, and
when the magnitude of the input signal increases above the preset level, the bias voltage at the gate of the first transistor decreases to a voltage lower than the first voltage.
20. The power amplifier of claim 18 , further comprising an amplitude injection circuit connected to the gate of the second transistor,
wherein the amplitude injection circuit is configured to produce an envelope signal from the pre-amplified signal, and to adjust an amplitude of the envelope signal based on a magnitude of the pre-amplified signal, to thereby generate and output a reshaped envelope signal to the gate of the second transistor.
21. The power amplifier of claim 20 , wherein the amplitude injection circuit is configured to adjust an amplitude of the reshaped envelope signal to a predetermined level if the magnitude of the pre-amplified signal is equal to or smaller than a preset level, and to adjust the amplitude of the reshaped envelope signal to a level higher than the predetermined level if the magnitude of the pre-amplified signal is greater than the preset level.
22. The power amplifier of claim 18 , wherein the first transistor is a common-source transistor.
23. The power amplifier of claim 18 , wherein the second transistor is a common-source transistor.