Semiconductor device that can cancel noise in bias line to which bias current flows

1. A method comprising:

supplying a first control signal to a first control line;

supplying a second control signal to a second control line;

controlling an amount of a bias current flowing to a bias line based on the first control signal and the second control signal, a first parasitic capacitance being formed between the first control line and the bias line and a second parasitic capacitance being formed between the second control line and the bias line;

changing at least one of the first control signal and the second control signal;

supplying an inversion signal of the first control signal to a first balance capacitor that includes one end coupled to the bias line and another end that receives the inversion signal of the first control signal;

substantially cancelling a potential fluctuation of the bias line caused by the changing of the at least one of the first control signal and the second control signal, wherein the potential fluctuation propagates via at least one of the first parasitic capacitance and the second parasitic capacitance corresponding to the at least one of the first control signal and the second control signal, and wherein a magnitude of the bias current or a level of a bias voltage into which the bias current is converted is a control parameter of a circuit to be controlled;

converting the bias current into the bias voltage; and

supplying the bias voltage to a control electrode of a bias transistor, wherein the bias transistor is coupled to a clock transmission line so that transmission characteristics of the clock transmission line are controlled based on the bias voltage.

2. The method as claimed in claim 1 , further comprising transmitting a clock signal on the clock transmission line.

3. A method comprising:

supplying a first control signal to a first control line;

supplying a second control signal to a second control line;

controlling an amount of a bias current flowing to a bias line based on the first control signal and the second control signal, a first parasitic capacitance being formed between the first control line and the bias line and a second parasitic capacitance being formed between the second control line and the bias line;

changing at least one of the first control signal and the second control signal;

supplying an inversion signal of the first control signal to a first balance capacitor that includes one end coupled to the bias line and another end that receives the inversion signal of the first control signal;

substantially cancelling a potential fluctuation of the bias line caused by the changing of the at least one of the first control signal and the second control signal, wherein the potential fluctuation propagates via at least one of the first parasitic capacitance and the second parasitic capacitance corresponding to the at least one of the first control signal and the second control signal, and wherein a magnitude of the bias current or a level of a bias voltage into which the bias current is converted is a control parameter of a circuit to be controlled;

converting the bias current into the bias voltage; and

supplying the bias voltage to a control electrode of a bias transistor, wherein the bias transistor is inserted between an inverter array and a power supply line so that transmission characteristics of the inverter array are controlled based on the bias voltage.

4. The method as claimed in claim 3 , wherein the power supply line provides an operating voltage for a delay locked loop.

5. The method as claimed in claim 3 , further comprising transmitting a clock signal from the inverter array.

6. A semiconductor device comprising:

a bias line to which a bias current flows;

a control unit configured to control an amount of the bias current based on a first control signal and a second control signal;

a first control line to which the first control signal is supplied, a first parasitic capacitance being formed between the first control line and the bias line;

a second control line to which the second control signal is supplied, a second parasitic capacitance being formed between the second control line and the bias line;

a cancel circuit configured to substantially cancel a potential fluctuation of the bias line caused by the changing of at least one of the first control signal and the second control signal, wherein the potential fluctuation propagates via at least one of the first parasitic capacitance and the second parasitic capacitance corresponding to the at least one of the first control signal and the second control signal, wherein a magnitude of the bias current or a level of a bias voltage into which the bias current is converted is a control parameter of a circuit to be controlled, and wherein the cancel circuit includes a first balance capacitor that includes one end coupled to the bias line and another end for receiving an inversion signal of the first control signal;

a current-to-voltage conversion circuit configured to convert the bias current into the bias voltage; and

a bias transistor that includes a control electrode to which the bias voltage is applied, wherein the bias transistor is coupled to a clock transmission line so that transmission characteristics of the clock transmission line are controlled based on the bias voltage.

7. The semiconductor device as claimed in claim 6 , wherein the clock transmission line transmits a clock signal.

8. A semiconductor device comprising:

a bias line to which a bias current flows;

a control unit configured to control an amount of the bias current based on a first control signal and a second control signal;

a first control line to which the first control signal is supplied, a first parasitic capacitance being formed between the first control line and the bias line;

a second control line to which the second control signal is supplied, a second parasitic capacitance being formed between the second control line and the bias line;

a cancel circuit configured to substantially cancel a potential fluctuation of the bias line caused by the changing of at least one of the first control signal and the second control signal, wherein the potential fluctuation propagates via at least one of the first parasitic capacitance and the second parasitic capacitance corresponding to the at least one of the first control signal and the second control signal, wherein a magnitude of the bias current or a level of a bias voltage into which the bias current is converted is a control parameter of a circuit to be controlled, and wherein the cancel circuit includes a first balance capacitor that includes one end coupled to the bias line and another end for receiving an inversion signal of the first control signal;

a current-to-voltage conversion circuit configured to convert the bias current into the bias voltage; and

a bias transistor that includes a control electrode to which the bias voltage is applied, wherein the bias transistor is inserted between an inverter array and a power supply line so that transmission characteristics of the inverter array are controlled based on the bias voltage.

9. The semiconductor device as claimed in claim 8 , wherein the power supply line provides an operating voltage for a delay locked loop.

10. The semiconductor device as claimed in claim 8 , wherein the inverter array transmits a clock signal.

11. The semiconductor device as claimed in claim 6 , wherein the first balance capacitor comprises a first transistor, wherein the another end of the first balance capacitor that receives the inversion signal of the first control signal is a control electrode of the first transistor, and wherein the end of the first balance capacitor coupled to the bias line comprises a node at which a source terminal and a drain terminal of the first transistor are short circuited.

12. A semiconductor device comprising:

a bias line to which a bias current flows;

a control unit configured to control an amount of the bias current based on a first control signal and a second control signal;

a first control line to which the first control signal is supplied, a first parasitic capacitance being formed between the first control line and the bias line;

a second control line to which the second control signal is supplied, a second parasitic capacitance being formed between the second control line and the bias line;

a cancel circuit configured to substantially cancel a potential fluctuation of the bias line caused by the changing of at least one of the first control signal and the second control signal, wherein the potential fluctuation propagates via at least one of the first parasitic capacitance and the second parasitic capacitance corresponding to the at least one of the first control signal and the second control signal, wherein a magnitude of the bias current or a level of a bias voltage into which the bias current is converted is a control parameter of a circuit to be controlled, and wherein the cancel circuit includes a first balance capacitor that includes one end coupled to the bias line and another end for receiving an inversion signal of the first control signal, wherein the cancel circuit includes a second balance capacitor that includes one end coupled to the bias line and another end for receiving an inversion signal of the second control signal.

13. The semiconductor device as claimed in claim 12 , wherein the second balance capacitor comprises a second transistor, wherein the another end of the second balance capacitor that receives the inversion signal of the second control signal is a control electrode of the second transistor, and wherein the end of the second balance capacitor coupled to the bias line comprises a node at which a source terminal and a drain terminal of the second transistor are short circuited.

14. The method as claimed in claim 1 , wherein the first balance capacitor includes a first transistor, wherein the another end of the first balance capacitor that receives the inversion signal of the first control signal is a control electrode of the first transistor, and wherein the end of the first balance capacitor coupled to the bias line comprises a node at which a source terminal and a drain terminal of the first transistor are short circuited.